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Thu, 21 Apr 2022 11:28:37 -0700 (PDT) Received: from mail.broadcom.net ([192.19.11.250]) by smtp.gmail.com with ESMTPSA id s62-20020a635e41000000b003a9eb7f65absm6509333pgb.85.2022.04.21.11.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 11:28:36 -0700 (PDT) From: Kamal Dasu To: ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, alcooperx@gmail.com Cc: f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kamal Dasu Subject: [PATCH 5/5] mmc: sdhci-brcmstb: Add ability to increase max clock rate for 72116b0 Date: Thu, 21 Apr 2022 14:28:03 -0400 Message-Id: <20220421182803.6495-6-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220421182803.6495-1-kdasu.kdev@gmail.com> References: <20220421182803.6495-1-kdasu.kdev@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220421_112840_136220_5484BB93 X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Al Cooper The 72116B0 has improved SDIO controllers that allow the max clock rate to be increased from a max of 100MHz to a max of 150MHz. The driver will need to get the clock and increase it's default rate and override the caps register, that still indicates a max of 100MHz. The new clock will be named "sdio_freq" in the DT node's "clock-names" list. The driver will use a DT property, "clock-frequency", to enable this functionality and will get the actual rate in MHz from the property to allow various speeds to be requested. Signed-off-by: Al Cooper Signed-off-by: Kamal Dasu --- drivers/mmc/host/sdhci-brcmstb.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index d5cb3e8978b2..4f3629a8e70a 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -250,6 +250,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) struct sdhci_pltfm_host *pltfm_host; const struct of_device_id *match; struct sdhci_brcmstb_priv *priv; + uint32_t base_clock_hz = 0; struct sdhci_host *host; struct resource *iomem; struct clk *clk; @@ -330,6 +331,30 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; + /* Change the base clock frequency if the DT property exists */ + if (device_property_read_u32(&pdev->dev, "clock-frequency", + &base_clock_hz) == 0) { + struct clk *master_clk; + u32 actual_clock_mhz; + + master_clk = devm_clk_get(&pdev->dev, "sdio_freq"); + if (IS_ERR(master_clk)) { + dev_warn(&pdev->dev, + "Clock for \"sdio_freq\" was not found\n"); + } else { + clk_set_rate(master_clk, base_clock_hz); + actual_clock_mhz = clk_get_rate(master_clk) / 1000000; + + host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; + host->caps |= + (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); + /* Disable presets because they are now incorrect */ + host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; + dev_dbg(&pdev->dev, + "Base Clock Frequency changed to %dMHz\n", + actual_clock_mhz); + } + } res = sdhci_brcmstb_add_host(host, priv); if (res) goto err;