From patchwork Fri Apr 22 06:01:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12822804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77C56C433F5 for ; Fri, 22 Apr 2022 06:10:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SNuMwYZ8kX/B5rHq0YTsnurlcseYDz9+xNltvJxK3oE=; b=jnnJ5E89E4wDIh xWgvjcVEZ45oOwTd0sPfmeZMdNIoszJ0teq/EyiJ5kHlSjY8LzUMHyXo4R08/yMy6hyL7phBiBQug z6b18mbkUZYIJCAHqthTsfXx6eIpphfTobdEqfl0xgnDNGgn7Sl/RzCAERhp3u1vf7qYU04H5m80J KWCxPw0vG84iv+vcefDRX2kc0lDm3L+P1Ifn/NC32k46QxyUQbi9W3dYvfmm7xneq+xn0Xsr0xiCH QXXVmbgJiJ59VZmn8VcKyOAXtGinffICupaSCHC8r/J4mLakSbQC68eFT5WzUVpXa3bkNmXBOqRFU EI6fXkcke+f4NpeybNxQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhmTz-00GOxY-9O; Fri, 22 Apr 2022 06:09:32 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhmTn-00GOrf-N0; Fri, 22 Apr 2022 06:09:21 +0000 X-UUID: 74d6c1d1af4542d0a18d07246142510d-20220421 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:d9194f99-1c55-4aa6-93df-9cf5854106b7, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9, CLOUDID:da7cbdef-06b0-4305-bfbf-554bfc9d151a, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 74d6c1d1af4542d0a18d07246142510d-20220421 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1209616100; Thu, 21 Apr 2022 23:09:11 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 23:02:00 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Apr 2022 14:01:59 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Apr 2022 14:01:59 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit Date: Fri, 22 Apr 2022 14:01:47 +0800 Message-ID: <20220422060152.13534-13-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220422060152.13534-1-rex-bc.chen@mediatek.com> References: <20220422060152.13534-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220421_230919_817426_FF616130 X-CRM114-Status: UNSURE ( 8.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support reset of infra_ao, add the bit definition for thermal/PCIe/SVS. Signed-off-by: Rex-BC Chen --- include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h index be9a7ca245b9..d5f3433175c1 100644 --- a/include/dt-bindings/reset/mt8192-resets.h +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -27,4 +27,14 @@ #define MT8192_TOPRGU_SW_RST_NUM 23 +/* INFRA RST0 */ +#define MT8192_INFRA_RST0_LVTS_AP_RST 0 +/* INFRA RST2 */ +#define MT8192_INFRA_RST2_PCIE_PHY_RST 15 +/* INFRA RST3 */ +#define MT8192_INFRA_RST3_PTP_RST 5 +/* INFRA RST4 */ +#define MT8192_INFRA_RST4_LVTS_MCU 12 +#define MT8192_INFRA_RST4_PCIE_TOP 1 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */