diff mbox series

[v2] arm64: document the boot requirements for MTE

Message ID 20220422202912.292039-1-pcc@google.com (mailing list archive)
State New, archived
Headers show
Series [v2] arm64: document the boot requirements for MTE | expand

Commit Message

Peter Collingbourne April 22, 2022, 8:29 p.m. UTC 
When booting the kernel we access system registers such as GCR_EL1
if MTE is supported. These accesses are defined to trap to EL3 if
SCR_EL3.ATA is disabled. Furthermore, tag accesses will not behave
as expected if SCR_EL3.ATA is not set, or if HCR_EL2.ATA is not set
and we were booted at EL1. Therefore, require that these bits are
enabled when appropriate.

Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://linux-review.googlesource.com/id/Iadcfd4dcd9ba3279b2813970b44d7485b0116709
---
v2:
- only required with FEAT_MTE2

 Documentation/arm64/booting.rst | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Catalin Marinas April 25, 2022, 4:19 p.m. UTC | #1 
On Fri, 22 Apr 2022 13:29:12 -0700, Peter Collingbourne wrote:
> When booting the kernel we access system registers such as GCR_EL1
> if MTE is supported. These accesses are defined to trap to EL3 if
> SCR_EL3.ATA is disabled. Furthermore, tag accesses will not behave
> as expected if SCR_EL3.ATA is not set, or if HCR_EL2.ATA is not set
> and we were booted at EL1. Therefore, require that these bits are
> enabled when appropriate.
> 
> [...]

Applied to arm64 (for-next/misc), thanks!

[1/1] arm64: document the boot requirements for MTE
      https://git.kernel.org/arm64/c/b6ba1a89f73f
diff mbox series

Patch

diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 29884b261aa9..8aefa1001ae5 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -350,6 +350,16 @@  Before jumping into the kernel, the following conditions must be met:
 
     - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
 
+  For CPUs with the Memory Tagging Extension feature (FEAT_MTE2):
+
+  - If EL3 is present:
+
+    - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
+
+  - If the kernel is entered at EL1 and EL2 is present:
+
+    - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
+
 The requirements described above for CPU mode, caches, MMUs, architected
 timers, coherency and system registers apply to all CPUs.  All CPUs must
 enter the kernel in the same exception level.  Where the values documented