From patchwork Wed Apr 27 03:09:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8886DC433EF for ; Wed, 27 Apr 2022 03:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eyAeCeztE7tZLlKofO1qNKdKPc5SEEDpwavr+O3vaFw=; b=YpNJjzl8bJm+Fb csiTGdpVVKXRtRpcilr7kUFVUDU5ZXs2kCAfauJbjGjfIvSVsyomtc9g1FMnbUWoNyPgATTqaRq6G fpqUpKx9rDvSZCslYPmMiVWJw5NChhAyuC7o3dzr1i/ga0zMm0bhGiukd8UdoBs6Ioz7FuEJANPPv b6x/AatGjBpOog6UeJMjT0Y4xv91CARg/rvVTHCP3ymuifBvzH8bmr7HY/G8AZSbUBQ4oahzQj971 7iTq6TXLSwvgACOu/Eupm6dev1VTJI2Z3Ucm6+y3F1PbRsWfNNbUAXHMV/PQQUJp9UHwRSO5HjMvP oOm5TvYFGSUImsPZzRPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njYGi-00HC92-LO; Wed, 27 Apr 2022 03:23:08 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1njYG6-00HBtf-G3; Wed, 27 Apr 2022 03:22:31 +0000 X-UUID: 53b85e9b7864480b98a16ce2224af47e-20220426 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:2aa3fcf1-7795-41cd-a011-50ec167685c3, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9, CLOUDID:6e719cc6-85ee-4ac1-ac05-bd3f1e72e732, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 53b85e9b7864480b98a16ce2224af47e-20220426 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 810139977; Tue, 26 Apr 2022 20:22:23 -0700 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Apr 2022 20:12:26 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:21 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 13/15] clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 Date: Wed, 27 Apr 2022 11:09:48 +0800 Message-ID: <20220427030950.23395-14-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_202230_553186_7224D1D9 X-CRM114-Status: GOOD ( 14.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The infra_ao reset is needed for MT8192 and MT8195. - Add mtk_clk_rst_desc for MT8192 and MT8195. - Add register reset controller function for MT8192 infra_ao. - Move definition of infra reset from cl-mt8183.c to reset.h because it's the same definition with MT8192 and MT8195. - Add new definition of infra reset_4 for MT8192 and MT8195. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt8183.c | 6 ------ drivers/clk/mediatek/clk-mt8192.c | 18 ++++++++++++++++++ drivers/clk/mediatek/clk-mt8195-infra_ao.c | 15 +++++++++++++++ drivers/clk/mediatek/reset.h | 7 +++++++ 4 files changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index c7d5ffacbd1d..40b53e15411d 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -18,12 +18,6 @@ #include -/* Infra global controller reset set register */ -#define INFRA_RST0_SET_OFFSET 0x120 -#define INFRA_RST1_SET_OFFSET 0x130 -#define INFRA_RST2_SET_OFFSET 0x140 -#define INFRA_RST3_SET_OFFSET 0x150 - static DEFINE_SPINLOCK(mt8183_clk_lock); static const struct mtk_fixed_clk top_fixed_clks[] = { diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index ab27cd66b866..add177eb17d2 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1114,6 +1114,20 @@ static const struct mtk_gate top_clks[] = { GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), }; +static u16 infra_ao_rst_ofs[] = { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_ao_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), +}; + #define MT8192_PLL_FMAX (3800UL * MHZ) #define MT8192_PLL_FMIN (1500UL * MHZ) #define MT8192_INTEGER_BITS 8 @@ -1239,6 +1253,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev) if (r) goto free_clk_data; + r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); + if (r) + goto free_clk_data; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 8ebe3b9415c4..4b7f21a6b93c 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -182,9 +182,24 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31), }; +static u16 infra_ao_rst_ofs[] = { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static struct mtk_clk_rst_desc infra_ao_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_ao_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), +}; + static const struct mtk_clk_desc infra_ao_desc = { .clks = infra_ao_clks, .num_clks = ARRAY_SIZE(infra_ao_clks), + .rst_desc = &infra_ao_rst_desc, }; static const struct of_device_id of_match_clk_mt8195_infra_ao[] = { diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 470588b82418..aebfb0ceabbe 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -11,6 +11,13 @@ #define RST_NR_PER_BANK 32 +/* Infra global controller reset set register */ +#define INFRA_RST0_SET_OFFSET 0x120 +#define INFRA_RST1_SET_OFFSET 0x130 +#define INFRA_RST2_SET_OFFSET 0x140 +#define INFRA_RST3_SET_OFFSET 0x150 +#define INFRA_RST4_SET_OFFSET 0x730 + /** * enum mtk_reset_version - Version of MediaTek clock reset controller. * @MTK_RST_SIMPLE: Use the same registers for bit set and clear.