From patchwork Wed Apr 27 11:25:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 12828666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75D56C433EF for ; Wed, 27 Apr 2022 11:27:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1EAknQ5xZeMD64lujf6zT9f+2jn0Cs5g6hN8zH9IQeg=; b=bj44cLu7Nrara4 TCrqiW4USI8WHesXsG3hXGC40YQ9d8KON5BxX1UY6DqHZ5FKB1L8KkKusHbRFcsH2LorZiyH504yc cbBdrjRZAtNOWTlM1I0FV8HGzGV55/FBvRgHYljCAo9G1wwnYei+TrrzONfJ5rCPdvzWIyiX7328X 03mynjvuuY0VNC6/A+nEPK/zuZbNw6EsI7U4Fdotwh1du8Okgvck7XwZqQTYFz41eFOy1SgSASXa+ imgwaGJzidhU/dnUjq8aphXo8qLVsWGYy7Qqm4mXFG6127ya542dxZ/Mn12b7PxxTHzq4YBrcysPW 0Or2Q3uVuf1HKOOdkgiA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njfoK-0014Vw-QB; Wed, 27 Apr 2022 11:26:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njfns-0014MC-Mi for linux-arm-kernel@lists.infradead.org; Wed, 27 Apr 2022 11:25:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A7AFFED1; Wed, 27 Apr 2022 04:25:50 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A26473F5A1; Wed, 27 Apr 2022 04:25:49 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski Cc: Liviu Dudau , Robin Murphy , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 03/11] dt-bindings: arm: sp810: convert to DT schema Date: Wed, 27 Apr 2022 12:25:20 +0100 Message-Id: <20220427112528.4097815-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220427112528.4097815-1-andre.przywara@arm.com> References: <20220427112528.4097815-1-andre.przywara@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220427_042552_873952_ACAD97F0 X-CRM114-Status: GOOD ( 14.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Arm SP810 IP is a "system controller", providing clocks, timer and a watchdog. Convert the DT binding to DT schema, to allow automatic validation. Signed-off-by: Andre Przywara --- .../devicetree/bindings/arm/sp810.txt | 46 ----------- .../devicetree/bindings/arm/sp810.yaml | 82 +++++++++++++++++++ 2 files changed, 82 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/sp810.txt create mode 100644 Documentation/devicetree/bindings/arm/sp810.yaml diff --git a/Documentation/devicetree/bindings/arm/sp810.txt b/Documentation/devicetree/bindings/arm/sp810.txt deleted file mode 100644 index 46652bf651478..0000000000000 --- a/Documentation/devicetree/bindings/arm/sp810.txt +++ /dev/null @@ -1,46 +0,0 @@ -SP810 System Controller ------------------------ - -Required properties: - -- compatible: standard compatible string for a Primecell peripheral, - see Documentation/devicetree/bindings/arm/primecell.yaml - for more details - should be: "arm,sp810", "arm,primecell" - -- reg: standard registers property, physical address and size - of the control registers - -- clock-names: from the common clock bindings, for more details see - Documentation/devicetree/bindings/clock/clock-bindings.txt; - should be: "refclk", "timclk", "apb_pclk" - -- clocks: from the common clock bindings, phandle and clock - specifier pairs for the entries of clock-names property - -- #clock-cells: from the common clock bindings; - should be: <1> - -- clock-output-names: from the common clock bindings; - should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3" - -- assigned-clocks: from the common clock binding; - should be: clock specifier for each output clock of this - provider node - -- assigned-clock-parents: from the common clock binding; - should be: phandle of input clock listed in clocks - property with the highest frequency - -Example: - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - - }; diff --git a/Documentation/devicetree/bindings/arm/sp810.yaml b/Documentation/devicetree/bindings/arm/sp810.yaml new file mode 100644 index 0000000000000..837f2bb3dbb42 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sp810.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sp810.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Express SP810 System Controller bindings + +maintainers: + - Andre Przywara + +description: |+ + The Arm SP810 system controller provides clocks, timers and a watchdog. + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + const: arm,sp810 + required: + - compatible + +properties: + compatible: + items: + - const: arm,sp810 + - const: arm,primecell + + reg: + maxItems: 1 + + clock-names: + items: + - const: refclk + - const: timclk + - const: apb_pclk + + clocks: + items: + - description: reference clock + - description: timer clock + - description: APB register access clock + + "#clock-cells": + const: 1 + + clock-output-names: + items: + - const: timerclken0 + - const: timerclken1 + - const: timerclken2 + - const: timerclken3 + + assigned-clocks: + minItems: 4 + + assigned-clock-parents: + minItems: 4 + +additionalProperties: false + +required: + - compatible + - reg + - "#clock-cells" + +examples: + - | + sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", + "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, + <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, + <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + };