| Message ID | 20220427180853.35970-2-kdasu.kdev@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mmc: sdhci-brcmstb: host controller clock enhancements | expand |
On Wed, 27 Apr 2022 at 20:09, Kamal Dasu <kdasu.kdev@gmail.com> wrote: > > From: Al Cooper <alcooperx@gmail.com> > > Re-organize the flags by basing the bit names on the flag that they > apply to. Also change the "flags" member in the "brcmstb_match_priv" > struct to const. > > Signed-off-by: Al Cooper <alcooperx@gmail.com> > Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> > Acked-by: Florian Fainelli <f.fainelli@gmail.com> > Acked-by: Adrian Hunter <adrian.hunter@intel.com> Applied for next, thanks! Kind regards Uffe > --- > drivers/mmc/host/sdhci-brcmstb.c | 32 ++++++++++++++++---------------- > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c > index f24623aac2db..244780481193 100644 > --- a/drivers/mmc/host/sdhci-brcmstb.c > +++ b/drivers/mmc/host/sdhci-brcmstb.c > @@ -18,20 +18,22 @@ > #define SDHCI_VENDOR 0x78 > #define SDHCI_VENDOR_ENHANCED_STRB 0x1 > > -#define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0) > -#define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1) > +#define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) > +#define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) > + > +#define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) > > #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 > > struct sdhci_brcmstb_priv { > void __iomem *cfg_regs; > - bool has_cqe; > + unsigned int flags; > }; > > struct brcmstb_match_priv { > void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); > struct sdhci_ops *ops; > - unsigned int flags; > + const unsigned int flags; > }; > > static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) > @@ -134,13 +136,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_7216 = { > }; > > static struct brcmstb_match_priv match_priv_7425 = { > - .flags = BRCMSTB_PRIV_FLAGS_NO_64BIT | > - BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, > + .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | > + BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, > .ops = &sdhci_brcmstb_ops, > }; > > static struct brcmstb_match_priv match_priv_7445 = { > - .flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, > + .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, > .ops = &sdhci_brcmstb_ops, > }; > > @@ -176,7 +178,7 @@ static int sdhci_brcmstb_add_host(struct sdhci_host *host, > bool dma64; > int ret; > > - if (!priv->has_cqe) > + if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) > return sdhci_add_host(host); > > dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); > @@ -225,7 +227,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > struct sdhci_brcmstb_priv *priv; > struct sdhci_host *host; > struct resource *iomem; > - bool has_cqe = false; > struct clk *clk; > int res; > > @@ -244,10 +245,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > return res; > > memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); > - if (device_property_read_bool(&pdev->dev, "supports-cqe")) { > - has_cqe = true; > - match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; > - } > brcmstb_pdata.ops = match_priv->ops; > host = sdhci_pltfm_init(pdev, &brcmstb_pdata, > sizeof(struct sdhci_brcmstb_priv)); > @@ -258,7 +255,10 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > > pltfm_host = sdhci_priv(host); > priv = sdhci_pltfm_priv(pltfm_host); > - priv->has_cqe = has_cqe; > + if (device_property_read_bool(&pdev->dev, "supports-cqe")) { > + priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; > + match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; > + } > > /* Map in the non-standard CFG registers */ > iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); > @@ -287,14 +287,14 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > * properties through mmc_of_parse(). > */ > host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); > - if (match_priv->flags & BRCMSTB_PRIV_FLAGS_NO_64BIT) > + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) > host->caps &= ~SDHCI_CAN_64BIT; > host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); > host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | > SDHCI_SUPPORT_DDR50); > host->quirks |= SDHCI_QUIRK_MISSING_CAPS; > > - if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT) > + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) > host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; > > res = sdhci_brcmstb_add_host(host, priv); > -- > 2.17.1 >
diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index f24623aac2db..244780481193 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -18,20 +18,22 @@ #define SDHCI_VENDOR 0x78 #define SDHCI_VENDOR_ENHANCED_STRB 0x1 -#define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0) -#define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1) +#define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) +#define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) + +#define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 struct sdhci_brcmstb_priv { void __iomem *cfg_regs; - bool has_cqe; + unsigned int flags; }; struct brcmstb_match_priv { void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); struct sdhci_ops *ops; - unsigned int flags; + const unsigned int flags; }; static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) @@ -134,13 +136,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_7216 = { }; static struct brcmstb_match_priv match_priv_7425 = { - .flags = BRCMSTB_PRIV_FLAGS_NO_64BIT | - BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, + .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | + BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, .ops = &sdhci_brcmstb_ops, }; static struct brcmstb_match_priv match_priv_7445 = { - .flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, + .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, .ops = &sdhci_brcmstb_ops, }; @@ -176,7 +178,7 @@ static int sdhci_brcmstb_add_host(struct sdhci_host *host, bool dma64; int ret; - if (!priv->has_cqe) + if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) return sdhci_add_host(host); dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); @@ -225,7 +227,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) struct sdhci_brcmstb_priv *priv; struct sdhci_host *host; struct resource *iomem; - bool has_cqe = false; struct clk *clk; int res; @@ -244,10 +245,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) return res; memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); - if (device_property_read_bool(&pdev->dev, "supports-cqe")) { - has_cqe = true; - match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; - } brcmstb_pdata.ops = match_priv->ops; host = sdhci_pltfm_init(pdev, &brcmstb_pdata, sizeof(struct sdhci_brcmstb_priv)); @@ -258,7 +255,10 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); priv = sdhci_pltfm_priv(pltfm_host); - priv->has_cqe = has_cqe; + if (device_property_read_bool(&pdev->dev, "supports-cqe")) { + priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; + match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; + } /* Map in the non-standard CFG registers */ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); @@ -287,14 +287,14 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) * properties through mmc_of_parse(). */ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); - if (match_priv->flags & BRCMSTB_PRIV_FLAGS_NO_64BIT) + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) host->caps &= ~SDHCI_CAN_64BIT; host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_DDR50); host->quirks |= SDHCI_QUIRK_MISSING_CAPS; - if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT) + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; res = sdhci_brcmstb_add_host(host, priv);