From patchwork Mon May 2 08:13:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 12833929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9AAF7C433F5 for ; Mon, 2 May 2022 08:17:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=peOchBwpcOTGr3WUjzy5QrYBzbJKVd9UHQpYP+zywkY=; b=qKg7cfP7XBzdMa cMjx2y2nuYlvQHutgEdR1MEkR2z5MJ6q8ktwptUVw1NpBMUSU13cDwalJCIxC81DnfPWEyHOlq0VY SnXi3uQUzxG53Wykl5zIMUCSHyMjytTG1RMyHsdEaiDjNCYJoyxuceWHmUDHy8f4yQ/yIXJ/CLpl9 F6oDsFzLoahkSvNtoIgfnajyxXeoGQYW+M2PGD13aO3TWEFNthMXxFD+0iWc9fRCHVu5DbX3QsHiE fK0nUpBjW3PKV2npCkegOu5xIzGsH/DsvIlnfetxEDief1t4bjkBx63xku07ZlOstWWppiwiYAxPV XvgPtrf5cPayX0t2wd3g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlRDQ-000GhP-TN; Mon, 02 May 2022 08:15:33 +0000 Received: from gandalf.ozlabs.org ([150.107.74.76]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlRCE-000Ful-TT; Mon, 02 May 2022 08:14:21 +0000 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4KsG8T4Zx9z4xXk; Mon, 2 May 2022 18:14:17 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4KsG8N2D3yz4x7Y; Mon, 2 May 2022 18:14:12 +1000 (AEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org Cc: Mark Brown , Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-aspeed@lists.ozlabs.org, Joel Stanley , Andrew Jeffery , Chin-Ting Kuo , devicetree@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , Tao Ren , Jae Hyun Yoo Subject: [PATCH v5 04/11] spi: aspeed: Add support for direct mapping Date: Mon, 2 May 2022 10:13:34 +0200 Message-Id: <20220502081341.203369-5-clg@kaod.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220502081341.203369-1-clg@kaod.org> References: <20220502081341.203369-1-clg@kaod.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220502_011420_091551_27DDC2E3 X-CRM114-Status: GOOD ( 17.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use direct mapping to read the flash device contents. This operation mode is called "Command mode" on Aspeed SoC SMC controllers. It uses a Control Register for the settings to apply when a memory operation is performed on the flash device mapping window. If the window is not big enough, fall back to the "User mode" to perform the read. Direct mapping for writes will come later when validated. Reviewed-by: Joel Stanley Tested-by: Joel Stanley Tested-by: Tao Ren Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater --- drivers/spi/spi-aspeed-smc.c | 68 ++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index cb5a0652e5a4..50cc7bd7ba3e 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -411,10 +411,78 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip) return chip->ahb_window_size ? 0 : -1; } +static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) +{ + struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master); + struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select]; + struct spi_mem_op *op = &desc->info.op_tmpl; + u32 ctl_val; + int ret = 0; + + chip->clk_freq = desc->mem->spi->max_speed_hz; + + /* Only for reads */ + if (op->data.dir != SPI_MEM_DATA_IN) + return -EOPNOTSUPP; + + if (desc->info.length > chip->ahb_window_size) + dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping", + chip->cs, chip->ahb_window_size >> 20); + + /* Define the default IO read settings */ + ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK; + ctl_val |= aspeed_spi_get_io_mode(op) | + op->cmd.opcode << CTRL_COMMAND_SHIFT | + CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth) | + CTRL_IO_MODE_READ; + + /* Tune 4BYTE address mode */ + if (op->addr.nbytes) { + u32 addr_mode = readl(aspi->regs + CE_CTRL_REG); + + if (op->addr.nbytes == 4) + addr_mode |= (0x11 << chip->cs); + else + addr_mode &= ~(0x11 << chip->cs); + writel(addr_mode, aspi->regs + CE_CTRL_REG); + } + + /* READ mode is the controller default setting */ + chip->ctl_val[ASPEED_SPI_READ] = ctl_val; + writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); + + dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n", + chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]); + + return ret; +} + +static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, + u64 offset, size_t len, void *buf) +{ + struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master); + struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select]; + + /* Switch to USER command mode if mapping window is too small */ + if (chip->ahb_window_size < offset + len) { + int ret; + + ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf); + if (ret < 0) + return ret; + } else { + memcpy_fromio(buf, chip->ahb_base + offset, len); + } + + return len; +} + static const struct spi_controller_mem_ops aspeed_spi_mem_ops = { .supports_op = aspeed_spi_supports_op, .exec_op = aspeed_spi_exec_op, .get_name = aspeed_spi_get_name, + .dirmap_create = aspeed_spi_dirmap_create, + .dirmap_read = aspeed_spi_dirmap_read, }; static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)