From patchwork Tue May 3 10:55:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12835657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87BDEC433EF for ; Tue, 3 May 2022 11:04:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FaI4dIR3x07kyjaeucH4/GmAO3rk0bwndOqZKWSIRX8=; b=B+bkALpYhhZ/A5 vTOpyCcEY8DnBWJZ63EQ51m5smiXRfIhsWfYVptviquueWxwesv402wDlGl8sXJdF3IRnp7eF7I89 3HcGrlg527V2/3K19BOqMgfhx4v2eoCdkQW2cNEOrTYjrbxZW9dyfOMT5RFXHBWO5BZbgg0uzIkQ9 u3SqPrGB2zC2/cDxEQgARBwMh2Co1pQLGrSzd4bV9Md4Iy6Lj5Jw4ULNf2itkkLpG1/DgRHOJbx3i KkWMOK9VgquSFhe5i5ivjhV/esc4XmQ20jokQOL9Zrd8l/hEb67ONXxJ8n/cSIRtQbD1NPq5+icjG pGlZT9RHwuDYr17N8bzw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlqJ0-005UH0-Tc; Tue, 03 May 2022 11:03:01 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlqCl-005Q71-9x for linux-arm-kernel@lists.infradead.org; Tue, 03 May 2022 10:56:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651575391; x=1683111391; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=SRrXglg6r6VWu9S1ahzrarbkehQWcyMubV3bZWXG/sk=; b=n9x2ClDZ1kLDchFN9S+gak5/ooRIOhAV0No3vljj/Y0H4JqP3JXsvgrA F+HCVpEoNrnXMOyju5N7ugE7uxff6xsLWrApPXU8krft5roHo1JIW9rBo rxTm9SUmcOcOCTOlYCAzESNSiP5tyZGGyAu7ySkVl2y7uaePw0qD13/mE Yv+X425EceYxqcIgfL3DmarbiXlx+5yDwocAMn2GxKgl/HSJKbyS1dRnt bI3J1q/bPu5ypdxaE75bylMtiDZPV6lE54tVtTgeAOMMXI9GSFpy73mlZ kfrnDxmX3V9C7zPvoe4tfGG6X0Oy6JtwrvwdeJq8d/IAWF85shOyToSCK w==; X-IronPort-AV: E=Sophos;i="5.91,195,1647327600"; d="scan'208";a="162127862" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 May 2022 03:56:30 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 3 May 2022 03:56:30 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 3 May 2022 03:56:25 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH 3/4] dt-bindings: mux: Add lan966 flexcom mux controller Date: Tue, 3 May 2022 16:25:27 +0530 Message-ID: <20220503105528.12824-4-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> References: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220503_035631_394117_FCAF880B X-CRM114-Status: GOOD ( 12.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds DT bindings documentation for lan966 flexcom mux controller. Signed-off-by: Kavyasree Kotagiri --- .../mux/microchip,lan966-flx-mux.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml diff --git a/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml new file mode 100644 index 000000000000..8b20f531781a --- /dev/null +++ b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/microchip,lan966-flx-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: microchip Lan966 Flexcom multiplexer bindings + +maintainers: + - Kavyasree Kotagiri + +description: |+ + The Microchip Lan966 have 5 Flexcoms. Each flexcom has 2 chip-selects + when operating in USART and SPI modes. + Each chip select of each flexcom can be mapped to 21 flexcom shared pins. + Define register offset and pin number to map a flexcom chip-select + to flexcom shared pin. + +properties: + compatible: + enum: + - microchip,lan966-flx-mux + + reg: + maxItems: 1 + + '#mux-control-cells': + const: 1 + + mux-offset-pin: + description: an array of register offset and flexcom shared pin(0-20). + +required: + - compatible + - '#mux-control-cells' + - mux-offset-pin + +additionalProperties: false + +examples: + - | + mux: mux-controller@e2004168 { + compatible = "microchip,lan966-flx-mux"; + reg = <0xe2004168 0x8>; + #mux-control-cells = <1>; + mux-offset-pin = + <0x18 9>; /* 0: flx3 cs0 offset, pin-9 */ + }; + + flx3 { + atmel,flexcom-mode = <2>; + mux-controls = <&mux 0>; + mux-control-names = "cs0"; + }; +...