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Wed, 04 May 2022 00:54:02 -0700 From: Piyush Mehta To: , , , , , , CC: , , , , , , Piyush Mehta Subject: [PATCH 2/2] usb: dwc3: xilinx: Add gpio-reset support Date: Wed, 4 May 2022 13:23:09 +0530 Message-ID: <20220504075309.6244-3-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220504075309.6244-1-piyush.mehta@xilinx.com> References: <20220504075309.6244-1-piyush.mehta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 41945fa2-ad94-4331-06f5-08da2da34ab1 X-MS-TrafficTypeDiagnostic: SN6PR02MB4528:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tTYWvmNtOTc7fI624irmPHSJKbxs39Kjh5F3d1WVdyEnRXtzdYC/9RzxaZR7cJAf4YCMfJpcII/+kdmNG29r6qTUkz6xX5x2Yvf1lvEnNwQRSBTPMB5jaFyR/FLUZpQEgZE1drTefcLD26x+C7tV5b6/FSDkJLxImayfUWfR+34ubCkwBVgCzPAlu3yimz10tzR+M5w9GMgg1DJ0RkCbk2LDsgFl21mMDy9XZ0dLaawEWaIxDkfCcebDWmJo0iKlIeC3YyPNjrNKmWol62heVJixXmvIYSpqBlgpgWQj4ihYl1Hj6dqaq1X53WkcpgMp+eRirjJ0mXvXDt/C5tArFXie3Z6q3Ne7aRI1AJsD2jH+mCG+aNa0ls26RqVK/CI6CityQT6sVpyEuxUw4TRhPJXKCGetCC3zSdjvsloJLZrwvNXL/vAvIBSi+WRFDgDtK7LcCxjngNFDzPH0Cutf0UO4WI+DSFBjBS8DXOgCfWEQOuo6PuL50Fa5S7hfm3faQ7k3VOIJaln0Cu9AZHAJVKYVpPKnqD8OXeaA1MFMtFUH0KKtzjGIw1F36ytCy6CAp+ZUmqTGMmBIFkIt9BNeXBHUBcE/2YhGpwNZcM+I+FBX32/W/oY2qYRdnFjLqXpT57hj7LqryOB/ROswZj47bQqGxLmU4YcPvoVwFFwWn7+RRTaQ9F/N+NQBaeucA4tG0q8cP9SF981auzZBqCx/XJHe3sAwdYfoxz1Vz3XOq6k= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(110136005)(44832011)(508600001)(54906003)(5660300002)(83380400001)(36860700001)(82310400005)(70586007)(9786002)(8936002)(2906002)(36756003)(316002)(6636002)(4326008)(8676002)(70206006)(7696005)(107886003)(2616005)(1076003)(186003)(47076005)(426003)(336012)(26005)(40460700003)(356005)(7636003)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2022 07:54:18.1600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41945fa2-ad94-4331-06f5-08da2da34ab1 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0037.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB4528 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_005423_017804_F117310B X-CRM114-Status: GOOD ( 16.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds a USB GPIO based reset for dwc3-xilinx driver. The PHY needs to be reset after the completion of phy initialization. As part of the reset, check for gpio-reset binding before toggling the pin. This feature is advantageous when the user toggle GPIO to trigger the ULPI-PHY reset. Delay of milliseconds is added in between low and high to meet the setup and hold time requirement of the reset. The reset-gpio error handling is added for error notification. Some GPIO controllers must be accessed using message-based buses, like I2C or SPI, to address this problem, updates GPIO access with sleep API. This reset is specific to the zynqMp. Signed-off-by: Piyush Mehta --- drivers/usb/dwc3/dwc3-xilinx.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c index a6f3a9b..67b237c 100644 --- a/drivers/usb/dwc3/dwc3-xilinx.c +++ b/drivers/usb/dwc3/dwc3-xilinx.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -98,6 +99,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data) { struct device *dev = priv_data->dev; struct reset_control *crst, *hibrst, *apbrst; + struct gpio_desc *reset_gpio; struct phy *usb3_phy; int ret = 0; u32 reg; @@ -201,6 +203,21 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data) } skip_usb3_phy: + /* ulpi reset via gpio-modepin or gpio-framework driver */ + reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(reset_gpio)) { + return dev_err_probe(dev, PTR_ERR(reset_gpio), + "Failed to request reset GPIO\n"); + } + + if (reset_gpio) { + /* Toggle ulpi to reset the phy. */ + gpiod_set_value_cansleep(reset_gpio, 1); + usleep_range(5000, 10000); + gpiod_set_value_cansleep(reset_gpio, 0); + usleep_range(5000, 10000); + } + /* * This routes the USB DMA traffic to go through FPD path instead * of reaching DDR directly. This traffic routing is needed to