diff mbox series

[09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols

Message ID 20220504122601.335495-10-y.oudjana@protonmail.com (mailing list archive)
State New, archived
Headers show
Series Mediatek MT6735 main clock and reset drivers | expand

Commit Message

Yassine Oudjana May 4, 2022, 12:25 p.m. UTC
From: Yassine Oudjana <y.oudjana@protonmail.com>

Export mtk_register_reset_controller and
mtk_register_reset_controller_set_clr to support building reset
drivers as modules.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
 drivers/clk/mediatek/reset.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Bo-Chen Chen May 4, 2022, 12:46 p.m. UTC | #1
On Wed, 2022-05-04 at 16:25 +0400, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
> 
> Export mtk_register_reset_controller and
> mtk_register_reset_controller_set_clr to support building reset
> drivers as modules.
> 
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> ---
>  drivers/clk/mediatek/reset.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/reset.c
> b/drivers/clk/mediatek/reset.c
> index bcec4b89f449..6c2effe6afef 100644
> --- a/drivers/clk/mediatek/reset.c
> +++ b/drivers/clk/mediatek/reset.c
> @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct
> device_node *np,
>  	mtk_register_reset_controller_common(np, num_regs, regofs,
>  		&mtk_reset_ops);
>  }
> +EXPORT_SYMBOL_GPL(mtk_register_reset_controller);
>  
>  void mtk_register_reset_controller_set_clr(struct device_node *np,
>  	unsigned int num_regs, int regofs)
> @@ -136,5 +137,6 @@ void mtk_register_reset_controller_set_clr(struct
> device_node *np,
>  	mtk_register_reset_controller_common(np, num_regs, regofs,
>  		&mtk_reset_ops_set_clr);
>  }
> +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr);
>  
>  MODULE_LICENSE("GPL");

Hello Yassine,

Thanks for your patch for mediatek clk reset.
But I have another series to cleanup mediatek clk reset drivers and
most of my patches are reviewed.
Please refer to
https://patchwork.kernel.org/project/linux-mediatek/list/?series=637849

BRs,
Rex
Yassine Oudjana May 4, 2022, 12:55 p.m. UTC | #2
On Wed, May 4 2022 at 20:46:22 +0800, Rex-BC Chen 
<rex-bc.chen@mediatek.com> wrote:
> On Wed, 2022-05-04 at 16:25 +0400, Yassine Oudjana wrote:
>>  From: Yassine Oudjana <y.oudjana@protonmail.com>
>> 
>>  Export mtk_register_reset_controller and
>>  mtk_register_reset_controller_set_clr to support building reset
>>  drivers as modules.
>> 
>>  Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>  ---
>>   drivers/clk/mediatek/reset.c | 2 ++
>>   1 file changed, 2 insertions(+)
>> 
>>  diff --git a/drivers/clk/mediatek/reset.c
>>  b/drivers/clk/mediatek/reset.c
>>  index bcec4b89f449..6c2effe6afef 100644
>>  --- a/drivers/clk/mediatek/reset.c
>>  +++ b/drivers/clk/mediatek/reset.c
>>  @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct
>>  device_node *np,
>>   	mtk_register_reset_controller_common(np, num_regs, regofs,
>>   		&mtk_reset_ops);
>>   }
>>  +EXPORT_SYMBOL_GPL(mtk_register_reset_controller);
>> 
>>   void mtk_register_reset_controller_set_clr(struct device_node *np,
>>   	unsigned int num_regs, int regofs)
>>  @@ -136,5 +137,6 @@ void 
>> mtk_register_reset_controller_set_clr(struct
>>  device_node *np,
>>   	mtk_register_reset_controller_common(np, num_regs, regofs,
>>   		&mtk_reset_ops_set_clr);
>>   }
>>  +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr);
>> 
>>   MODULE_LICENSE("GPL");
> 
> Hello Yassine,
> 
> Thanks for your patch for mediatek clk reset.
> But I have another series to cleanup mediatek clk reset drivers and
> most of my patches are reviewed.
> Please refer to
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=637849

Great! In that case I'll rebase my patches onto your series and see
if anything is missing.

Thanks,
Yassine
diff mbox series

Patch

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index bcec4b89f449..6c2effe6afef 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -129,6 +129,7 @@  void mtk_register_reset_controller(struct device_node *np,
 	mtk_register_reset_controller_common(np, num_regs, regofs,
 		&mtk_reset_ops);
 }
+EXPORT_SYMBOL_GPL(mtk_register_reset_controller);
 
 void mtk_register_reset_controller_set_clr(struct device_node *np,
 	unsigned int num_regs, int regofs)
@@ -136,5 +137,6 @@  void mtk_register_reset_controller_set_clr(struct device_node *np,
 	mtk_register_reset_controller_common(np, num_regs, regofs,
 		&mtk_reset_ops_set_clr);
 }
+EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr);
 
 MODULE_LICENSE("GPL");