Message ID | 20220506181034.2001548-7-l.stach@pengutronix.de (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | i.MX8MP HDMI support | expand |
[...] > +static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) > +{ > + struct fsl_samsung_hdmi_phy *phy; > + int ret; > + > + phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); > + if (!phy) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, phy); > + phy->dev = &pdev->dev; > + > + phy->regs = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(phy->regs)) > + return PTR_ERR(phy->regs); > + > + phy->apbclk = devm_clk_get(phy->dev, "apb"); > + if (IS_ERR(phy->apbclk)) > + return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), > + "failed to get apb clk\n"); > + > + phy->refclk = devm_clk_get(phy->dev, "ref"); > + if (IS_ERR(phy->refclk)) > + return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), > + "failed to get ref clk\n"); > + > + ret = clk_prepare_enable(phy->apbclk); > + if (ret) { > + dev_err(phy->dev, "failed to enable apbclk\n"); > + return ret; > + } dev_err_probe() here too ?
On 06-05-22, 20:10, Lucas Stach wrote: > This adds the driver for the Samsung HDMI PHY found on the > i.MX8MP SoC. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/phy/freescale/Kconfig | 6 + > drivers/phy/freescale/Makefile | 1 + > drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 1078 ++++++++++++++++++ > 3 files changed, 1085 insertions(+) > create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c > > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig > index f9c54cd02036..e88cc2212370 100644 > --- a/drivers/phy/freescale/Kconfig > +++ b/drivers/phy/freescale/Kconfig > @@ -26,6 +26,12 @@ config PHY_FSL_IMX8M_PCIE > Enable this to add support for the PCIE PHY as found on > i.MX8M family of SOCs. > > +config PHY_FSL_SAMSUNG_HDMI_PHY > + tristate "Samsung HDMI PHY support" > + depends on OF && HAS_IOMEM > + help > + Enable this to add support for the Samsung HDMI PHY in i.MX8MP. > + > endif > > config PHY_FSL_LYNX_28G > diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile > index 3518d5dbe8a7..46a26929376d 100644 > --- a/drivers/phy/freescale/Makefile > +++ b/drivers/phy/freescale/Makefile > @@ -2,4 +2,5 @@ > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o > obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o > +obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o > obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o > diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > new file mode 100644 > index 000000000000..6d20a5ce44e6 > --- /dev/null > +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > @@ -0,0 +1,1078 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2020 NXP > + * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de> > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > + > +#define HDMI_TX_CONTROL0 0x200 > +#define HDMI_TX_CONTROL_PHY_PWRDWN BIT(3) > + > +#define PHY_REG_33 0x84 > +#define REG33_MODE_SET_DONE BIT(7) > +#define REG33_FIX_DA BIT(1) > + > +#define PHY_REG_34 0x88 > +#define REG34_PHY_READY BIT(7) > +#define REG34_PLL_LOCK BIT(6) > +#define REG34_PHY_CLK_READY BIT(5) > + > + > +#define PHY_PLL_REGS_NUM 48 > + > +struct phy_config { > + u32 clk_rate; > + u8 regs[PHY_PLL_REGS_NUM]; > +}; > + > +const struct phy_config phy_pll_cfg[] = { > + { 22250000, { > + 0x00, 0xD1, 0x4B, 0xF1, 0x89, 0x88, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x15, 0x25, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, So we have only opaque register values we program for each rate...? No documentation for these registers? Also, will these be same across different SoC and boards as well..? Typically tuning parameters will differ for each board... > + }, > + }, { > + 23750000, { > + 0x00, 0xD1, 0x50, 0xF1, 0x86, 0x85, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x03, 0x25, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + },{ > + 24000000, { > + 0x00, 0xD1, 0x50, 0xF0, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x01, 0x25, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + },{ > + 24024000, { > + 0x00, 0xD1, 0x50, 0xF1, 0x99, 0x02, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x00, 0x25, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 25175000, { > + 0x00, 0xD1, 0x54, 0xFC, 0xCC, 0x91, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xF5, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 25200000, { > + 0x00, 0xD1, 0x54, 0xF0, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xF4, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 26750000, { > + 0x00, 0xD1, 0x5A, 0xF2, 0x89, 0x88, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE6, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 27000000, { > + 0x00, 0xD1, 0x5A, 0xF0, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 27027000, { > + 0x00, 0xD1, 0x5A, 0xF2, 0xFD, 0x0C, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 29500000, { > + 0x00, 0xD1, 0x62, 0xF4, 0x95, 0x08, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xD1, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 30750000, { > + 0x00, 0xD1, 0x66, 0xF4, 0x82, 0x01, 0x88, 0x45, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xC8, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 30888000, { > + 0x00, 0xD1, 0x66, 0xF4, 0x99, 0x18, 0x88, 0x45, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xC7, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 33750000, { > + 0x00, 0xD1, 0x70, 0xF4, 0x82, 0x01, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xB7, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 35000000, { > + 0x00, 0xD1, 0x58, 0xB8, 0x8B, 0x88, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xB0, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 36000000, { > + 0x00, 0xD1, 0x5A, 0xB0, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xAB, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 36036000, { > + 0x00, 0xD1, 0x5A, 0xB2, 0xFD, 0x0C, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xAB, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 40000000, { > + 0x00, 0xD1, 0x64, 0xB0, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x9A, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 43200000, { > + 0x00, 0xD1, 0x5A, 0x90, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8F, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 43243200, { > + 0x00, 0xD1, 0x5A, 0x92, 0xFD, 0x0C, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8F, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 44500000, { > + 0x00, 0xD1, 0x5C, 0x92, 0x98, 0x11, 0x84, 0x41, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x8B, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 47000000, { > + 0x00, 0xD1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x83, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 47500000, { > + 0x00, 0xD1, 0x63, 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0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 254000000, { > + 0x00, 0xD1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xC2, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 277500000, { > + 0x00, 0xD1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4D, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xB2, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 288000000, { > + 0x00, 0xD1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xAB, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, { > + 297000000, { > + 0x00, 0xD1, 0x7B, 0x15, 0x84, 0x03, 0x90, 0x45, > + 0x4F, 0x30, 0x33, 0x65, 0x30, 0xA6, 0x24, 0x80, > + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, > + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, > + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, > + }, > + }, > +}; > + > +struct fsl_samsung_hdmi_phy { > + struct device *dev; > + void __iomem *regs; > + struct clk *apbclk; > + struct clk *refclk; > + > + /* clk provider */ > + struct clk_hw hw; > + const struct phy_config *cur_cfg; > +}; > + > +static inline struct fsl_samsung_hdmi_phy * > +to_fsl_samsung_hdmi_phy(struct clk_hw *hw) > +{ > + return container_of(hw, struct fsl_samsung_hdmi_phy, hw); > +} > + > +static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, > + const struct phy_config *cfg) > +{ > + int i, ret; > + u8 val; > + > + /* HDMI PHY init */ > + writeb(REG33_FIX_DA, phy->regs + PHY_REG_33); > + > + for (i = 0; i < PHY_PLL_REGS_NUM; i++) > + writeb(cfg->regs[i], phy->regs + i * 4); > + > + writeb(REG33_FIX_DA | REG33_MODE_SET_DONE , phy->regs + PHY_REG_33); > + > + ret = readb_poll_timeout(phy->regs + PHY_REG_34, val, > + val & REG34_PLL_LOCK, > + 50, 20000); > + if (ret) > + dev_err(phy->dev, "PLL failed to lock\n"); > + > + return ret; > +} > + > +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); > + > + if (!phy->cur_cfg) > + return 74250000; > + > + return phy->cur_cfg->clk_rate; > +} > + > +static long phy_clk_round_rate(struct clk_hw *hw, > + unsigned long rate, unsigned long *parent_rate) > +{ > + int i; > + > + for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) > + if (phy_pll_cfg[i].clk_rate <= rate) > + return phy_pll_cfg[i].clk_rate; > + > + return -EINVAL; > +} > + > +static int phy_clk_set_rate(struct clk_hw *hw, > + unsigned long rate, unsigned long parent_rate) > +{ > + struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); > + int i; > + > + for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) > + if (phy_pll_cfg[i].clk_rate <= rate) > + break; > + > + if (i < 0) > + return -EINVAL; > + > + phy->cur_cfg = &phy_pll_cfg[i]; > + > + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); > +} > + > +static const struct clk_ops phy_clk_ops = { > + .recalc_rate = phy_clk_recalc_rate, > + .round_rate = phy_clk_round_rate, > + .set_rate = phy_clk_set_rate, > +}; > + > +static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy) > +{ > + struct device *dev = phy->dev; > + struct device_node *np = dev->of_node; > + struct clk_init_data init; > + const char *parent_name; > + struct clk *phyclk; > + int ret; > + > + parent_name = __clk_get_name(phy->refclk); > + > + init.parent_names = &parent_name; > + init.num_parents = 1; > + init.flags = 0; > + init.name = "hdmi_pclk"; > + init.ops = &phy_clk_ops; > + > + phy->hw.init = &init; > + > + phyclk = devm_clk_register(dev, &phy->hw); > + if (IS_ERR(phyclk)) > + return dev_err_probe(dev, PTR_ERR(phyclk), > + "failed to register clock\n"); > + > + ret = of_clk_add_provider(np, of_clk_src_simple_get, phyclk); > + if (ret) > + return dev_err_probe(dev, ret, > + "failed to register clock provider\n"); > + > + return 0; > +} > + > +static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) > +{ > + struct fsl_samsung_hdmi_phy *phy; > + int ret; > + > + phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); > + if (!phy) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, phy); > + phy->dev = &pdev->dev; > + > + phy->regs = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(phy->regs)) > + return PTR_ERR(phy->regs); > + > + phy->apbclk = devm_clk_get(phy->dev, "apb"); > + if (IS_ERR(phy->apbclk)) > + return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), > + "failed to get apb clk\n"); > + > + phy->refclk = devm_clk_get(phy->dev, "ref"); > + if (IS_ERR(phy->refclk)) > + return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), > + "failed to get ref clk\n"); > + > + ret = clk_prepare_enable(phy->apbclk); > + if (ret) { > + dev_err(phy->dev, "failed to enable apbclk\n"); > + return ret; > + } > + > + pm_runtime_get_noresume(phy->dev); > + pm_runtime_set_active(phy->dev); > + pm_runtime_enable(phy->dev); > + > + ret = phy_clk_register(phy); > + if (ret) { > + dev_err(&pdev->dev, "register clk failed\n"); > + goto register_clk_failed; > + } > + > + pm_runtime_put(phy->dev); > + > + return 0; > + > +register_clk_failed: > + clk_disable_unprepare(phy->apbclk); > + > + return ret; > +} > + > +static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev) > +{ > + of_clk_del_provider(pdev->dev.of_node); > + > + return 0; > +} > + > +#ifdef CONFIG_PM > +static int fsl_samsung_hdmi_phy_suspend(struct device *dev) > +{ > + struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev); > + > + clk_disable_unprepare(phy->apbclk); > + > + return 0; > +} > + > +static int fsl_samsung_hdmi_phy_resume(struct device *dev) > +{ > + struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev); > + int ret = 0; > + > + ret = clk_prepare_enable(phy->apbclk); > + if (ret) { > + dev_err(phy->dev, "failed to enable apbclk\n"); > + return ret; > + } > + > + if (phy->cur_cfg) > + ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); > + > + return ret; > + > +} > +#endif > + > +static const struct dev_pm_ops fsl_samsung_hdmi_phy_pm_ops = { > + SET_RUNTIME_PM_OPS(fsl_samsung_hdmi_phy_suspend, > + fsl_samsung_hdmi_phy_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, > + pm_runtime_force_resume) > +}; > + > +static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = { > + { > + .compatible = "fsl,imx8mp-hdmi-phy", > + }, { > + /* sentinel */ > + } > +}; > +MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match); > + > +static struct platform_driver fsl_samsung_hdmi_phy_driver = { > + .probe = fsl_samsung_hdmi_phy_probe, > + .remove = fsl_samsung_hdmi_phy_remove, > + .driver = { > + .name = "fsl-samsung-hdmi-phy", > + .of_match_table = fsl_samsung_hdmi_phy_of_match, > + .pm = &fsl_samsung_hdmi_phy_pm_ops, > + }, > +}; > +module_platform_driver(fsl_samsung_hdmi_phy_driver); > + > +MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>"); > +MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.30.2 > > > -- > linux-phy mailing list > linux-phy@lists.infradead.org > https://lists.infradead.org/mailman/listinfo/linux-phy
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index f9c54cd02036..e88cc2212370 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -26,6 +26,12 @@ config PHY_FSL_IMX8M_PCIE Enable this to add support for the PCIE PHY as found on i.MX8M family of SOCs. +config PHY_FSL_SAMSUNG_HDMI_PHY + tristate "Samsung HDMI PHY support" + depends on OF && HAS_IOMEM + help + Enable this to add support for the Samsung HDMI PHY in i.MX8MP. + endif config PHY_FSL_LYNX_28G diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index 3518d5dbe8a7..46a26929376d 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -2,4 +2,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o +obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c new file mode 100644 index 000000000000..6d20a5ce44e6 --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -0,0 +1,1078 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de> + */ + +#include <linux/clk-provider.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> + +#define HDMI_TX_CONTROL0 0x200 +#define HDMI_TX_CONTROL_PHY_PWRDWN BIT(3) + +#define PHY_REG_33 0x84 +#define REG33_MODE_SET_DONE BIT(7) +#define REG33_FIX_DA BIT(1) + +#define PHY_REG_34 0x88 +#define REG34_PHY_READY BIT(7) +#define REG34_PLL_LOCK BIT(6) +#define REG34_PHY_CLK_READY BIT(5) + + +#define PHY_PLL_REGS_NUM 48 + +struct phy_config { + u32 clk_rate; + u8 regs[PHY_PLL_REGS_NUM]; +}; + +const struct phy_config phy_pll_cfg[] = { + { 22250000, { + 0x00, 0xD1, 0x4B, 0xF1, 0x89, 0x88, 0x80, 0x40, + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x15, 0x25, 0x80, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, + }, + }, { + 23750000, { + 0x00, 0xD1, 0x50, 0xF1, 0x86, 0x85, 0x80, 0x40, + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x03, 0x25, 0x80, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, + }, + },{ + 24000000, { + 0x00, 0xD1, 0x50, 0xF0, 0x00, 0x00, 0x80, 0x00, + 0x4F, 0x30, 0x33, 0x65, 0x00, 0x01, 0x25, 0x80, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 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0x30, 0x33, 0x65, 0x30, 0xA6, 0x24, 0x80, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32, + 0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, + }, + }, +}; + +struct fsl_samsung_hdmi_phy { + struct device *dev; + void __iomem *regs; + struct clk *apbclk; + struct clk *refclk; + + /* clk provider */ + struct clk_hw hw; + const struct phy_config *cur_cfg; +}; + +static inline struct fsl_samsung_hdmi_phy * +to_fsl_samsung_hdmi_phy(struct clk_hw *hw) +{ + return container_of(hw, struct fsl_samsung_hdmi_phy, hw); +} + +static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, + const struct phy_config *cfg) +{ + int i, ret; + u8 val; + + /* HDMI PHY init */ + writeb(REG33_FIX_DA, phy->regs + PHY_REG_33); + + for (i = 0; i < PHY_PLL_REGS_NUM; i++) + writeb(cfg->regs[i], phy->regs + i * 4); + + writeb(REG33_FIX_DA | REG33_MODE_SET_DONE , phy->regs + PHY_REG_33); + + ret = readb_poll_timeout(phy->regs + PHY_REG_34, val, + val & REG34_PLL_LOCK, + 50, 20000); + if (ret) + dev_err(phy->dev, "PLL failed to lock\n"); + + return ret; +} + +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); + + if (!phy->cur_cfg) + return 74250000; + + return phy->cur_cfg->clk_rate; +} + +static long phy_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + int i; + + for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) + if (phy_pll_cfg[i].clk_rate <= rate) + return phy_pll_cfg[i].clk_rate; + + return -EINVAL; +} + +static int phy_clk_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); + int i; + + for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) + if (phy_pll_cfg[i].clk_rate <= rate) + break; + + if (i < 0) + return -EINVAL; + + phy->cur_cfg = &phy_pll_cfg[i]; + + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); +} + +static const struct clk_ops phy_clk_ops = { + .recalc_rate = phy_clk_recalc_rate, + .round_rate = phy_clk_round_rate, + .set_rate = phy_clk_set_rate, +}; + +static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy) +{ + struct device *dev = phy->dev; + struct device_node *np = dev->of_node; + struct clk_init_data init; + const char *parent_name; + struct clk *phyclk; + int ret; + + parent_name = __clk_get_name(phy->refclk); + + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = 0; + init.name = "hdmi_pclk"; + init.ops = &phy_clk_ops; + + phy->hw.init = &init; + + phyclk = devm_clk_register(dev, &phy->hw); + if (IS_ERR(phyclk)) + return dev_err_probe(dev, PTR_ERR(phyclk), + "failed to register clock\n"); + + ret = of_clk_add_provider(np, of_clk_src_simple_get, phyclk); + if (ret) + return dev_err_probe(dev, ret, + "failed to register clock provider\n"); + + return 0; +} + +static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) +{ + struct fsl_samsung_hdmi_phy *phy; + int ret; + + phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + platform_set_drvdata(pdev, phy); + phy->dev = &pdev->dev; + + phy->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->regs)) + return PTR_ERR(phy->regs); + + phy->apbclk = devm_clk_get(phy->dev, "apb"); + if (IS_ERR(phy->apbclk)) + return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), + "failed to get apb clk\n"); + + phy->refclk = devm_clk_get(phy->dev, "ref"); + if (IS_ERR(phy->refclk)) + return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), + "failed to get ref clk\n"); + + ret = clk_prepare_enable(phy->apbclk); + if (ret) { + dev_err(phy->dev, "failed to enable apbclk\n"); + return ret; + } + + pm_runtime_get_noresume(phy->dev); + pm_runtime_set_active(phy->dev); + pm_runtime_enable(phy->dev); + + ret = phy_clk_register(phy); + if (ret) { + dev_err(&pdev->dev, "register clk failed\n"); + goto register_clk_failed; + } + + pm_runtime_put(phy->dev); + + return 0; + +register_clk_failed: + clk_disable_unprepare(phy->apbclk); + + return ret; +} + +static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + + return 0; +} + +#ifdef CONFIG_PM +static int fsl_samsung_hdmi_phy_suspend(struct device *dev) +{ + struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev); + + clk_disable_unprepare(phy->apbclk); + + return 0; +} + +static int fsl_samsung_hdmi_phy_resume(struct device *dev) +{ + struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev); + int ret = 0; + + ret = clk_prepare_enable(phy->apbclk); + if (ret) { + dev_err(phy->dev, "failed to enable apbclk\n"); + return ret; + } + + if (phy->cur_cfg) + ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); + + return ret; + +} +#endif + +static const struct dev_pm_ops fsl_samsung_hdmi_phy_pm_ops = { + SET_RUNTIME_PM_OPS(fsl_samsung_hdmi_phy_suspend, + fsl_samsung_hdmi_phy_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = { + { + .compatible = "fsl,imx8mp-hdmi-phy", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match); + +static struct platform_driver fsl_samsung_hdmi_phy_driver = { + .probe = fsl_samsung_hdmi_phy_probe, + .remove = fsl_samsung_hdmi_phy_remove, + .driver = { + .name = "fsl-samsung-hdmi-phy", + .of_match_table = fsl_samsung_hdmi_phy_of_match, + .pm = &fsl_samsung_hdmi_phy_pm_ops, + }, +}; +module_platform_driver(fsl_samsung_hdmi_phy_driver); + +MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>"); +MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver"); +MODULE_LICENSE("GPL v2");
This adds the driver for the Samsung HDMI PHY found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/phy/freescale/Kconfig | 6 + drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 1078 ++++++++++++++++++ 3 files changed, 1085 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c