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[v1,2/6] arm64/sve: Add Perf extensions documentation

Message ID 20220509144257.1623063-3-james.clark@arm.com (mailing list archive)
State New, archived
Headers show
Series perf: arm64: Support for Dwarf unwinding through SVE functions | expand

Commit Message

James Clark May 9, 2022, 2:42 p.m. UTC 
Document that the VG register is available in Perf samples

Signed-off-by: James Clark <james.clark@arm.com>
---
 Documentation/arm64/sve.rst | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Mark Brown May 9, 2022, 3:45 p.m. UTC | #1 
On Mon, May 09, 2022 at 03:42:50PM +0100, James Clark wrote:

> +* Its value is equivalent to the current vector length (VL) in bits divided by
> +  64.

Please explicitly say that this is the current *SVE* vector length,
given that with SME entering streaming mode means we have SVE registers
with the current streaming vector length which may be different to the
SVE vector length it is possible that someone may read the above as
referring to the vector length that applies to the current Z/P registers.
diff mbox series

Patch

diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst
index 9d9a4de5bc34..67e65bf66883 100644
--- a/Documentation/arm64/sve.rst
+++ b/Documentation/arm64/sve.rst
@@ -402,6 +402,24 @@  The regset data starts with struct user_sve_header, containing:
 * Modifying the system default vector length does not affect the vector length
   of any existing process or thread that does not make an execve() call.
 
+10.  Perf extensions
+--------------------------------
+
+* The arm64 specific DWARF standard [5] added the VG (Vector Granule) register
+  at index 46. This register is used for DWARF unwinding when variable length
+  SVE registers are pushed onto the stack.
+
+* Its value is equivalent to the current vector length (VL) in bits divided by
+  64.
+
+* The value is included in Perf samples in the regs[46] field if
+  PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set.
+
+* The value is the current value at the time the sample was taken, and it can
+  change over time.
+
+* If the system doesn't support SVE when perf_event_open is called with these
+  settings, the event will fail to open.
 
 Appendix A.  SVE programmer's model (informative)
 =================================================
@@ -543,3 +561,5 @@  References
     http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
     http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
     Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
+
+[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst