From patchwork Mon May 9 14:42:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 12843708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F145FC433F5 for ; Mon, 9 May 2022 14:44:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ce2jjFjnmpkeTfowfXV1eYq/uXrWXYFq0KS9CkN6fKg=; b=bcInD6lEi3f+f/ yqzqz6lwVD3xPl7LdJPhtpg6aUhpeWPBbH6xOoeyVdNFhYb+6YfLC2YU2J3vz/xafeDz3PUK1kTdp hOZju3qJN9qhOe6t+m0/8poCNXfIWsubvVCcrNaQqiIFkyvNABTEmFsaNTK1XFqRI77rcf1qKarXx Xi67QXdRfTQyGHhFpkUP3XPR6YmB+UjI/ZdyK+3aNyhnKhkvhXb8zjpgdNEh6a3UflPFRkim4Ey7j lHD6/uUOwf8S2W3Q0lap/RgJ0kTLzJbnDclwJkGLZp3xXDur03lGPJ1uDL/0pgvSrLr6gYrtJeoeL gYz1WuDX5Cm1MDf1wzVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1no4c2-00EuTv-42; Mon, 09 May 2022 14:43:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1no4bo-00EuOg-7h for linux-arm-kernel@lists.infradead.org; Mon, 09 May 2022 14:43:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE8F21480; Mon, 9 May 2022 07:43:34 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.4.213]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9F3353F73D; Mon, 9 May 2022 07:43:32 -0700 (PDT) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, broonie@kernel.org Cc: german.gomez@arm.com, James Clark , John Garry , Will Deacon , Mathieu Poirier , Leo Yan , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-doc@vger.kernel.org Subject: [PATCH v1 2/6] arm64/sve: Add Perf extensions documentation Date: Mon, 9 May 2022 15:42:50 +0100 Message-Id: <20220509144257.1623063-3-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220509144257.1623063-1-james.clark@arm.com> References: <20220509144257.1623063-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220509_074336_390775_5CDD3468 X-CRM114-Status: GOOD ( 12.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document that the VG register is available in Perf samples Signed-off-by: James Clark --- Documentation/arm64/sve.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst index 9d9a4de5bc34..67e65bf66883 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arm64/sve.rst @@ -402,6 +402,24 @@ The regset data starts with struct user_sve_header, containing: * Modifying the system default vector length does not affect the vector length of any existing process or thread that does not make an execve() call. +10. Perf extensions +-------------------------------- + +* The arm64 specific DWARF standard [5] added the VG (Vector Granule) register + at index 46. This register is used for DWARF unwinding when variable length + SVE registers are pushed onto the stack. + +* Its value is equivalent to the current vector length (VL) in bits divided by + 64. + +* The value is included in Perf samples in the regs[46] field if + PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set. + +* The value is the current value at the time the sample was taken, and it can + change over time. + +* If the system doesn't support SVE when perf_event_open is called with these + settings, the event will fail to open. Appendix A. SVE programmer's model (informative) ================================================= @@ -543,3 +561,5 @@ References http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html Procedure Call Standard for the ARM 64-bit Architecture (AArch64) + +[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst