From patchwork Tue May 10 01:52:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 12844399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD9DBC433F5 for ; Tue, 10 May 2022 01:55:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ujv3tJ4S38KphnquzdwqBZLs0HCnWFmBprYF3JoPrOk=; b=k1e/Z7NrC+R52f wAqyc2WaupWpigfBxJlENKjrqDiUpYFqjDh9RzUctQ02tDBczWqz30Sd6WRrYauQjRn5QD+47jYFj CagVmK77QWKLOfFTHWTlcJch5uieLlaX0jOzaIZkHODHVQZkDFo0jWgP3lEWfgWuFVKv6D6P1sZhV sdM4SnKEJki7wgw0chOSKnrt/oUFe/2P1U28DA5cRjGIKq0vl0H9oN+UhdFuS12dzMT8Ue5Mp1F/5 v8RVqE5MZ7Z5IIHsf4FppBuVp87iBNwuZVF5d5nZTM+yy6XrpMpDSz5BXt7xPttkp0VnJ/UWssKoL KhfdssPJIo6/UPkGDvKw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1noF4i-00H46k-4E; Tue, 10 May 2022 01:54:08 +0000 Received: from mo-csw1514.securemx.jp ([210.130.202.153] helo=mo-csw.securemx.jp) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1noF3h-00H3lH-JH for linux-arm-kernel@lists.infradead.org; Tue, 10 May 2022 01:53:09 +0000 Received: by mo-csw.securemx.jp (mx-mo-csw1514) id 24A1qjhs003919; Tue, 10 May 2022 10:52:45 +0900 X-Iguazu-Qid: 34tMbOxKUJOM4eLy9N X-Iguazu-QSIG: v=2; s=0; t=1652147564; q=34tMbOxKUJOM4eLy9N; m=R1jSCNcHLEoaFBNyV6StyWjZNtQapTTo6wL7OMiuW9k= Received: from imx12-a.toshiba.co.jp (imx12-a.toshiba.co.jp [61.202.160.135]) by relay.securemx.jp (mx-mr1511) id 24A1qivq019637 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 10 May 2022 10:52:44 +0900 From: Nobuhiro Iwamatsu To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Arnd Bergmann , Olof Johansson , yuji2.ishikawa@toshiba.co.jp, Nobuhiro Iwamatsu Subject: [PATCH 4/9] arm64: dts: visconti: Update the clock providers for SPI Date: Tue, 10 May 2022 10:52:24 +0900 X-TSB-HOP2: ON Message-Id: <20220510015229.139818-5-nobuhiro1.iwamatsu@toshiba.co.jp> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220510015229.139818-1-nobuhiro1.iwamatsu@toshiba.co.jp> References: <20220510015229.139818-1-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220509_185305_894202_90DC8A3F X-CRM114-Status: UNSURE ( 9.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Remove fixed clock and source common clock for SPI. Signed-off-by: Nobuhiro Iwamatsu --- .../dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 2 -- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 21 ++++++++++++------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index adfe8406c24c..0c8321022a73 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -25,8 +25,6 @@ &spi0_pins { &spi0 { status = "okay"; - clocks = <&clk300mhz>, <&clk150mhz>; - clock-names = "sspclk", "apb_pclk"; mmc-slot@0 { compatible = "mmc-spi-slot"; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 6050796a1678..196cda7b5d90 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -143,13 +143,6 @@ clk125mhz: clk125mhz { clock-output-names = "clk125mhz"; }; - clk150mhz: clk150mhz { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - clock-output-names = "clk150mhz"; - }; - clk300mhz: clk300mhz { compatible = "fixed-clock"; clock-frequency = <300000000>; @@ -395,6 +388,8 @@ spi0: spi@28140000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -407,6 +402,8 @@ spi1: spi@28141000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -419,6 +416,8 @@ spi2: spi@28142000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI2>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -431,6 +430,8 @@ spi3: spi@28143000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI3>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -443,6 +444,8 @@ spi4: spi@28144000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI4>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -455,6 +458,8 @@ spi5: spi@28145000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI5>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -467,6 +472,8 @@ spi6: spi@28146000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI6>; + clock-names = "apb_pclk"; status = "disabled"; };