| Message ID | 20220510094457.4070764-2-claudiu.beznea@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | nvmem: add Microchip OTP controller | expand |
On 10/05/2022 11:44, Claudiu Beznea wrote: > Document Microchip OTP controller. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > .../bindings/nvmem/microchip-otpc.yaml | 55 +++++++++++++++++++ > include/dt-bindings/nvmem/microchip,otpc.h | 18 ++++++ > 2 files changed, 73 insertions(+) > create mode 100644 Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml > create mode 040000 include/dt-bindings/nvmem > create mode 100644 include/dt-bindings/nvmem/microchip,otpc.h > > diff --git a/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml > new file mode 100644 > index 000000000000..a8df7fee5c2b > --- /dev/null > +++ b/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml vendor,device.yaml device should not be a wildcard but first compatible, so microchip,sama7g5-otpc.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/nvmem/microchip-otpc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip SAMA7G5 OTP Controller (OTPC) device tree bindings s/device tree bindings// > + > +maintainers: > + - Claudiu Beznea <claudiu.beznea@microchip.com> > + > +description: | > + This binding represents the OTP controller found on SAMA7G5 SoC. Entire description is duplicating title. Please describe the hardware or skip it. OTOH, you should mention the header, for example in description. > + > +allOf: > + - $ref: "nvmem.yaml#" > + > +properties: > + compatible: > + items: > + - const: microchip,sama7g5-otpc > + - const: syscon > + > + reg: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 These come from nvmem.yaml. > + > +required: > + - compatible > + - reg > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/at91.h> How the clock is used here? > + #include <dt-bindings/nvmem/microchip,otpc.h> > + > + otpc: efuse@e8c00000 { > + compatible = "microchip,sama7g5-otpc", "syscon"; > + reg = <0xe8c00000 0xec>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + temperature_calib: calib@1 { > + reg = <OTP_PKT(1) OTP_PKT_SAMA7G5_TEMP_CALIB_LEN>; > + }; > + }; > + > +... > diff --git a/include/dt-bindings/nvmem/microchip,otpc.h b/include/dt-bindings/nvmem/microchip,otpc.h > new file mode 100644 > index 000000000000..44b6ed3b8f18 > --- /dev/null > +++ b/include/dt-bindings/nvmem/microchip,otpc.h > @@ -0,0 +1,18 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Same license as bindings. > + > +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H > +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H > + > +/* > + * Need to have it as a multiple of 4 as NVMEM memory is registered with > + * stride = 4. > + */ > +#define OTP_PKT(id) ((id) * 4) Do I get it correctly - the offset or register address is now part of a binding? You write here "id", however you use it as part of "reg", so it's confusing. > + > +/* > + * Temperature calibration packet length for SAMA7G5: 1 words header, > + * 18 words payload. > + */ > +#define OTP_PKT_SAMA7G5_TEMP_CALIB_LEN (19 * 4) Length of some memory region also does not look like job for bindings. Best regards, Krzysztof
On 11.05.2022 18:27, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 10/05/2022 11:44, Claudiu Beznea wrote: >> Document Microchip OTP controller. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> >> --- >> .../bindings/nvmem/microchip-otpc.yaml | 55 +++++++++++++++++++ >> include/dt-bindings/nvmem/microchip,otpc.h | 18 ++++++ >> 2 files changed, 73 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml >> create mode 040000 include/dt-bindings/nvmem >> create mode 100644 include/dt-bindings/nvmem/microchip,otpc.h >> >> diff --git a/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml >> new file mode 100644 >> index 000000000000..a8df7fee5c2b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml > > vendor,device.yaml > device should not be a wildcard but first compatible, so > microchip,sama7g5-otpc.yaml OK > > >> @@ -0,0 +1,55 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/nvmem/microchip-otpc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Microchip SAMA7G5 OTP Controller (OTPC) device tree bindings > > s/device tree bindings// OK > >> + >> +maintainers: >> + - Claudiu Beznea <claudiu.beznea@microchip.com> >> + >> +description: | >> + This binding represents the OTP controller found on SAMA7G5 SoC. > > Entire description is duplicating title. Please describe the hardware or > skip it. OK > > OTOH, you should mention the header, for example in description. > >> + >> +allOf: >> + - $ref: "nvmem.yaml#" >> + >> +properties: >> + compatible: >> + items: >> + - const: microchip,sama7g5-otpc >> + - const: syscon >> + >> + reg: >> + maxItems: 1 >> + >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + const: 1 > > These come from nvmem.yaml. OK > >> + >> +required: >> + - compatible >> + - reg >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/at91.h> > > How the clock is used here? This is garbage. I forgot it here. > >> + #include <dt-bindings/nvmem/microchip,otpc.h> >> + >> + otpc: efuse@e8c00000 { >> + compatible = "microchip,sama7g5-otpc", "syscon"; >> + reg = <0xe8c00000 0xec>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + temperature_calib: calib@1 { >> + reg = <OTP_PKT(1) OTP_PKT_SAMA7G5_TEMP_CALIB_LEN>; >> + }; >> + }; >> + >> +... >> diff --git a/include/dt-bindings/nvmem/microchip,otpc.h b/include/dt-bindings/nvmem/microchip,otpc.h >> new file mode 100644 >> index 000000000000..44b6ed3b8f18 >> --- /dev/null >> +++ b/include/dt-bindings/nvmem/microchip,otpc.h >> @@ -0,0 +1,18 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ > > Same license as bindings. OK > >> + >> +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H >> +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H >> + >> +/* >> + * Need to have it as a multiple of 4 as NVMEM memory is registered with >> + * stride = 4. >> + */ >> +#define OTP_PKT(id) ((id) * 4) > > Do I get it correctly - the offset or register address is now part of a > binding? You write here "id", however you use it as part of "reg", so > it's confusing. I agree that reg should describe the offset in OTP memory and its the length for a cell. However this OTP memory is organized into packets (this is how hardware is designed), the 1st one being the boot configuration packet, the 2nd one being temperature calibration data. At the moment Microchip provides only these 2 packets in OTP memory. Boot configuration packet may vary in length thus it may change the offset the temperature calibration packet resides to. If this happen and we use offset based addressing in device trees then the solution will not work all the time. OTP hardware is designed to work with packets. For a packet being in memory at offset 0x0E as follows: offset OTP Memory layout . . . ... . . . 0x0E +-----------+ <--- packet X | header X | 0x12 +-----------+ | payload X | 0x16 | | | | 0x1A | | +-----------+ . . . ... . . . requesting from software data at address 0x16 (through OTP control registers) will return the whole packet starting at offset 0x0E. Same things happens when requesting data at offset 0x0E, 0x12, 0x1A. Thus, as underlying hardware returns to software chunks of 4 bytes though data registers the driver has been registered with stride = 4. The OTP_PKT() macro expects packet identifier (starting from 0), multiplies it by 4 to be able to pass the NVMEM subsystem accordingly, then the driver which manages a list of the available packets divides this value by 4 and gets the packet ID and the proper offset in memory for the requested packet ID. The intention was to have the OTP_PKT() macro here to be used in device trees for simpler way of describing different cells in this OTP memory. Also, using OTP_PKT() abstraction looked to me closer to the reality (although the computed value is not reflecting this, it is only an abstraction to be able to pass the NVMEM subsystem). Would you prefer to have raw values instead of using this macro? Adapting the subsystem for this kind of devices is also an option if Srinivas thinks like this. > >> + >> +/* >> + * Temperature calibration packet length for SAMA7G5: 1 words header, >> + * 18 words payload. >> + */ >> +#define OTP_PKT_SAMA7G5_TEMP_CALIB_LEN (19 * 4) > > Length of some memory region also does not look like job for bindings. I added it here to be able to have the same macro in DT and consumer drivers taking as example iio drivers that uses this approach to describe IIO channel identifiers. I can remove it and use necessary macros in the consumer drivers, if it's better this way. Thank you for your review, Claudiu Beznea > > Best regards, > Krzysztof
On 12/05/2022 09:17, Claudiu.Beznea@microchip.com wrote: >> >>> + >>> +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H >>> +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H >>> + >>> +/* >>> + * Need to have it as a multiple of 4 as NVMEM memory is registered with >>> + * stride = 4. >>> + */ >>> +#define OTP_PKT(id) ((id) * 4) >> >> Do I get it correctly - the offset or register address is now part of a >> binding? You write here "id", however you use it as part of "reg", so >> it's confusing. > > I agree that reg should describe the offset in OTP memory and its the > length for a cell. > > However this OTP memory is organized into packets (this is how hardware is > designed), the 1st one being the boot configuration packet, the 2nd one > being temperature calibration data. At the moment Microchip provides only > these 2 packets in OTP memory. Boot configuration packet may vary in length > thus it may change the offset the temperature calibration packet resides > to. If this happen and we use offset based addressing in device trees then > the solution will not work all the time. > > OTP hardware is designed to work with packets. For a packet being in memory > at offset 0x0E as follows: > > offset OTP Memory layout > > . . > . ... . > . . > 0x0E +-----------+ <--- packet X > | header X | > 0x12 +-----------+ > | payload X | > 0x16 | | > | | > 0x1A | | > +-----------+ > . . > . ... . > . . > > requesting from software data at address 0x16 (through OTP control > registers) will return the whole packet starting at offset 0x0E. Same > things happens when requesting data at offset 0x0E, 0x12, 0x1A. > > Thus, as underlying hardware returns to software chunks of 4 bytes though > data registers the driver has been registered with stride = 4. The > OTP_PKT() macro expects packet identifier (starting from 0), multiplies it > by 4 to be able to pass the NVMEM subsystem accordingly, then the driver > which manages a list of the available packets divides this value by 4 and > gets the packet ID and the proper offset in memory for the requested packet ID. > > The intention was to have the OTP_PKT() macro here to be used in device > trees for simpler way of describing different cells in this OTP memory. > Also, using OTP_PKT() abstraction looked to me closer to the reality > (although the computed value is not reflecting this, it is only an > abstraction to be able to pass the NVMEM subsystem). > > Would you prefer to have raw values instead of using this macro? Macro is a nice idea if it can be stable. I understood that length of packets depends on hardware, so this part could be stable. But what about number of packets, so the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN below? You wrote "Boot configuration packet may vary in length", so it could be changed by Microchip? Once this value is stored in the bindings, it is not supposed to change. > > Adapting the subsystem for this kind of devices is also an option if > Srinivas thinks like this. > >> >>> + >>> +/* >>> + * Temperature calibration packet length for SAMA7G5: 1 words header, >>> + * 18 words payload. >>> + */ >>> +#define OTP_PKT_SAMA7G5_TEMP_CALIB_LEN (19 * 4) >> >> Length of some memory region also does not look like job for bindings. > > I added it here to be able to have the same macro in DT and consumer > drivers taking as example iio drivers that uses this approach to describe > IIO channel identifiers. I can remove it and use necessary macros in the > consumer drivers, if it's better this way. Best regards, Krzysztof
On 12.05.2022 10:54, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 12/05/2022 09:17, Claudiu.Beznea@microchip.com wrote: >>> >>>> + >>>> +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H >>>> +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H >>>> + >>>> +/* >>>> + * Need to have it as a multiple of 4 as NVMEM memory is registered with >>>> + * stride = 4. >>>> + */ >>>> +#define OTP_PKT(id) ((id) * 4) >>> >>> Do I get it correctly - the offset or register address is now part of a >>> binding? You write here "id", however you use it as part of "reg", so >>> it's confusing. >> >> I agree that reg should describe the offset in OTP memory and its the >> length for a cell. >> >> However this OTP memory is organized into packets (this is how hardware is >> designed), the 1st one being the boot configuration packet, the 2nd one >> being temperature calibration data. At the moment Microchip provides only >> these 2 packets in OTP memory. Boot configuration packet may vary in length >> thus it may change the offset the temperature calibration packet resides >> to. If this happen and we use offset based addressing in device trees then >> the solution will not work all the time. >> >> OTP hardware is designed to work with packets. For a packet being in memory >> at offset 0x0E as follows: >> >> offset OTP Memory layout >> >> . . >> . ... . >> . . >> 0x0E +-----------+ <--- packet X >> | header X | >> 0x12 +-----------+ >> | payload X | >> 0x16 | | >> | | >> 0x1A | | >> +-----------+ >> . . >> . ... . >> . . >> >> requesting from software data at address 0x16 (through OTP control >> registers) will return the whole packet starting at offset 0x0E. Same >> things happens when requesting data at offset 0x0E, 0x12, 0x1A. >> >> Thus, as underlying hardware returns to software chunks of 4 bytes though >> data registers the driver has been registered with stride = 4. The >> OTP_PKT() macro expects packet identifier (starting from 0), multiplies it >> by 4 to be able to pass the NVMEM subsystem accordingly, then the driver >> which manages a list of the available packets divides this value by 4 and >> gets the packet ID and the proper offset in memory for the requested packet ID. >> >> The intention was to have the OTP_PKT() macro here to be used in device >> trees for simpler way of describing different cells in this OTP memory. >> Also, using OTP_PKT() abstraction looked to me closer to the reality >> (although the computed value is not reflecting this, it is only an >> abstraction to be able to pass the NVMEM subsystem). >> >> Would you prefer to have raw values instead of using this macro? > > Macro is a nice idea if it can be stable. I understood that length of > packets depends on hardware, so this part could be stable. But what > about number of packets, so the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN below? The OTP_PKT_SAMA7G5_TEMP_CALIB_LEN here is the length of thermal calibration packet. This length is fixed and will not be changed. After these 2 packets (provided by Microchip) user may further flash any number of packets and use them as they wish. Driver is in charge of scanning the NVMEM for the available packets and prepare a list with their IDs and their starting offsets in NVMEM memory such that when it receives a read request it will be able to decode the packet offset based on packet identifier. In case different number of packets are available in NVMEM for different kind of setups (boards) these could also be referenced in board specific DT using OTP_PKT() macro and with proper length (which will depend on what user flashed). > You wrote "Boot configuration packet may vary in length", so it could be > changed by Microchip? Yes, between chip revisions its length could be changed. > > Once this value is stored in the bindings, it is not supposed to change. I agree! > >> >> Adapting the subsystem for this kind of devices is also an option if >> Srinivas thinks like this. >> >>> >>>> + >>>> +/* >>>> + * Temperature calibration packet length for SAMA7G5: 1 words header, >>>> + * 18 words payload. >>>> + */ >>>> +#define OTP_PKT_SAMA7G5_TEMP_CALIB_LEN (19 * 4) >>> >>> Length of some memory region also does not look like job for bindings. >> >> I added it here to be able to have the same macro in DT and consumer >> drivers taking as example iio drivers that uses this approach to describe >> IIO channel identifiers. I can remove it and use necessary macros in the >> consumer drivers, if it's better this way. > > > > Best regards, > Krzysztof
On 12/05/2022 17:31, Claudiu.Beznea@microchip.com wrote: >> >> Macro is a nice idea if it can be stable. I understood that length of >> packets depends on hardware, so this part could be stable. But what >> about number of packets, so the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN below? > > The OTP_PKT_SAMA7G5_TEMP_CALIB_LEN here is the length of thermal > calibration packet. This length is fixed and will not be changed. > > After these 2 packets (provided by Microchip) user may further flash any > number of packets and use them as they wish. > > Driver is in charge of scanning the NVMEM for the available packets and > prepare a list with their IDs and their starting offsets in NVMEM memory > such that when it receives a read request it will be able to decode the > packet offset based on packet identifier. > > In case different number of packets are available in NVMEM for different > kind of setups (boards) these could also be referenced in board specific DT > using OTP_PKT() macro and with proper length (which will depend on what > user flashed). > >> You wrote "Boot configuration packet may vary in length", so it could be >> changed by Microchip? > > Yes, between chip revisions its length could be changed. Chip revisions like different board compatibles thus different bindings/macro values? If not, then maybe better skip the length out of bindings and just provide the first macro. Best regards, Krzysztof
On 12.05.2022 18:35, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 12/05/2022 17:31, Claudiu.Beznea@microchip.com wrote: > >>> >>> Macro is a nice idea if it can be stable. I understood that length of >>> packets depends on hardware, so this part could be stable. But what >>> about number of packets, so the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN below? >> >> The OTP_PKT_SAMA7G5_TEMP_CALIB_LEN here is the length of thermal >> calibration packet. This length is fixed and will not be changed. >> >> After these 2 packets (provided by Microchip) user may further flash any >> number of packets and use them as they wish. >> >> Driver is in charge of scanning the NVMEM for the available packets and >> prepare a list with their IDs and their starting offsets in NVMEM memory >> such that when it receives a read request it will be able to decode the >> packet offset based on packet identifier. >> >> In case different number of packets are available in NVMEM for different >> kind of setups (boards) these could also be referenced in board specific DT >> using OTP_PKT() macro and with proper length (which will depend on what >> user flashed). >> >>> You wrote "Boot configuration packet may vary in length", so it could be >>> changed by Microchip? >> >> Yes, between chip revisions its length could be changed. > > Chip revisions like different board compatibles thus different > bindings/macro values? Not necessarily. It may happen that only ROM code to be updated (1st stage bootloader) end everything else on Linux side to be able to run as is. Or to just fix some bugs in different IPs. Things that will not necessarily need adding new compatibles for the new chip. And it may happen that new chip revisions to be populated on previous board revisions. > Chip revisions like different board compatibles thus different > *macro* values? If you're referring to the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN macro, this is established that will remain fixed b/w revisions. This is the length of the 2nd packet in NVMEM (that is of interest for thermal management). Only the length of the 1st packet may change. And addressing the NVMEM with packet id based index should take care of temperature calibration NVMEM DT binding to work all the time. > If not, then maybe better skip the length out of > bindings and just provide the first macro. As far as I know the length is part of the way the NVMEM cells are described in DT: it needs the offset in memory (for the data to be retrieved) and its length. Thank you, Claudiu Beznea > > > > Best regards, > Krzysztof > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 12/05/2022 18:04, Claudiu.Beznea@microchip.com wrote: > On 12.05.2022 18:35, Krzysztof Kozlowski wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> On 12/05/2022 17:31, Claudiu.Beznea@microchip.com wrote: >> >>>> >>>> Macro is a nice idea if it can be stable. I understood that length of >>>> packets depends on hardware, so this part could be stable. But what >>>> about number of packets, so the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN below? >>> >>> The OTP_PKT_SAMA7G5_TEMP_CALIB_LEN here is the length of thermal >>> calibration packet. This length is fixed and will not be changed. >>> >>> After these 2 packets (provided by Microchip) user may further flash any >>> number of packets and use them as they wish. >>> >>> Driver is in charge of scanning the NVMEM for the available packets and >>> prepare a list with their IDs and their starting offsets in NVMEM memory >>> such that when it receives a read request it will be able to decode the >>> packet offset based on packet identifier. >>> >>> In case different number of packets are available in NVMEM for different >>> kind of setups (boards) these could also be referenced in board specific DT >>> using OTP_PKT() macro and with proper length (which will depend on what >>> user flashed). >>> >>>> You wrote "Boot configuration packet may vary in length", so it could be >>>> changed by Microchip? >>> >>> Yes, between chip revisions its length could be changed. >> >> Chip revisions like different board compatibles thus different >> bindings/macro values? > > Not necessarily. It may happen that only ROM code to be updated (1st stage > bootloader) end everything else on Linux side to be able to run as is. Or > to just fix some bugs in different IPs. Things that will not necessarily > need adding new compatibles for the new chip. And it may happen that new > chip revisions to be populated on previous board revisions. > >> Chip revisions like different board compatibles thus different >> *macro* values? > > If you're referring to the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN macro, this is > established that will remain fixed b/w revisions. This is the length of the > 2nd packet in NVMEM (that is of interest for thermal management). > > Only the length of the 1st packet may change. And addressing the NVMEM with > packet id based index should take care of temperature calibration NVMEM DT > binding to work all the time. > >> If not, then maybe better skip the length out of >> bindings and just provide the first macro. > > As far as I know the length is part of the way the NVMEM cells are > described in DT: it needs the offset in memory (for the data to be > retrieved) and its length. In DT yes, but now you put the length in the bindings. It means DTS must have exactly that value and cannot use anything more. It's the same as hard-coding unit addresses in the bindings. Best regards, Krzysztof
On 13.05.2022 10:49, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 12/05/2022 18:04, Claudiu.Beznea@microchip.com wrote: >> On 12.05.2022 18:35, Krzysztof Kozlowski wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> On 12/05/2022 17:31, Claudiu.Beznea@microchip.com wrote: >>> >>>>> >>>>> Macro is a nice idea if it can be stable. I understood that length of >>>>> packets depends on hardware, so this part could be stable. But what >>>>> about number of packets, so the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN below? >>>> >>>> The OTP_PKT_SAMA7G5_TEMP_CALIB_LEN here is the length of thermal >>>> calibration packet. This length is fixed and will not be changed. >>>> >>>> After these 2 packets (provided by Microchip) user may further flash any >>>> number of packets and use them as they wish. >>>> >>>> Driver is in charge of scanning the NVMEM for the available packets and >>>> prepare a list with their IDs and their starting offsets in NVMEM memory >>>> such that when it receives a read request it will be able to decode the >>>> packet offset based on packet identifier. >>>> >>>> In case different number of packets are available in NVMEM for different >>>> kind of setups (boards) these could also be referenced in board specific DT >>>> using OTP_PKT() macro and with proper length (which will depend on what >>>> user flashed). >>>> >>>>> You wrote "Boot configuration packet may vary in length", so it could be >>>>> changed by Microchip? >>>> >>>> Yes, between chip revisions its length could be changed. >>> >>> Chip revisions like different board compatibles thus different >>> bindings/macro values? >> >> Not necessarily. It may happen that only ROM code to be updated (1st stage >> bootloader) end everything else on Linux side to be able to run as is. Or >> to just fix some bugs in different IPs. Things that will not necessarily >> need adding new compatibles for the new chip. And it may happen that new >> chip revisions to be populated on previous board revisions. >> >>> Chip revisions like different board compatibles thus different >>> *macro* values? >> >> If you're referring to the OTP_PKT_SAMA7G5_TEMP_CALIB_LEN macro, this is >> established that will remain fixed b/w revisions. This is the length of the >> 2nd packet in NVMEM (that is of interest for thermal management). >> >> Only the length of the 1st packet may change. And addressing the NVMEM with >> packet id based index should take care of temperature calibration NVMEM DT >> binding to work all the time. >> >>> If not, then maybe better skip the length out of >>> bindings and just provide the first macro. >> >> As far as I know the length is part of the way the NVMEM cells are >> described in DT: it needs the offset in memory (for the data to be >> retrieved) and its length. > > In DT yes, but now you put the length in the bindings. It means DTS must > have exactly that value and cannot use anything more. It's the same as > hard-coding unit addresses in the bindings. I see. I will provide only the OTP_PKT() macro in bindings as you suggested. Thank you, Claudiu Beznea > > > Best regards, > Krzysztof
diff --git a/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml new file mode 100644 index 000000000000..a8df7fee5c2b --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/microchip-otpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAMA7G5 OTP Controller (OTPC) device tree bindings + +maintainers: + - Claudiu Beznea <claudiu.beznea@microchip.com> + +description: | + This binding represents the OTP controller found on SAMA7G5 SoC. + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + items: + - const: microchip,sama7g5-otpc + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/at91.h> + #include <dt-bindings/nvmem/microchip,otpc.h> + + otpc: efuse@e8c00000 { + compatible = "microchip,sama7g5-otpc", "syscon"; + reg = <0xe8c00000 0xec>; + #address-cells = <1>; + #size-cells = <1>; + + temperature_calib: calib@1 { + reg = <OTP_PKT(1) OTP_PKT_SAMA7G5_TEMP_CALIB_LEN>; + }; + }; + +... diff --git a/include/dt-bindings/nvmem/microchip,otpc.h b/include/dt-bindings/nvmem/microchip,otpc.h new file mode 100644 index 000000000000..44b6ed3b8f18 --- /dev/null +++ b/include/dt-bindings/nvmem/microchip,otpc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H + +/* + * Need to have it as a multiple of 4 as NVMEM memory is registered with + * stride = 4. + */ +#define OTP_PKT(id) ((id) * 4) + +/* + * Temperature calibration packet length for SAMA7G5: 1 words header, + * 18 words payload. + */ +#define OTP_PKT_SAMA7G5_TEMP_CALIB_LEN (19 * 4) + +#endif
Document Microchip OTP controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- .../bindings/nvmem/microchip-otpc.yaml | 55 +++++++++++++++++++ include/dt-bindings/nvmem/microchip,otpc.h | 18 ++++++ 2 files changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/microchip-otpc.yaml create mode 040000 include/dt-bindings/nvmem create mode 100644 include/dt-bindings/nvmem/microchip,otpc.h