From patchwork Mon May 16 00:54:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 12850178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE3B2C433EF for ; Mon, 16 May 2022 00:57:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+bITybUnMC7IpQsh2/uwZDYPptY8FWBx0bnx0ZhkAm8=; b=fE1nwfHp5rAzmH xaKOSpQn2NvD9eKq3EW9eknID64jwNzdf4xRlroPKfV/AdoW3sywdDg1OH8lDttpL2YNceDYshSrM yAdYRtfggRqlhowSWNfgvBHXTe5rG6E7aLWpHu8W5NXMCtSnxgXlm/AVd5XilK14ob/V2WEFyC/XD TMBKG0r9uNXfU9lvDPE9nZkAA3CLrJF7a7fGTAAo+BncyL0epAuPAIqPVSmRoX4PTSOkcUgVvHdST 8fs2phXqcEL2UF5ESNDKkA0kbgGjXP4s2wOr6dX0HQL5tkHzuw2mbYLTBwYQbkRbcr5zeZGWkFump pPPodVQQ4lJP27izMogw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqP1c-005RXd-Ur; Mon, 16 May 2022 00:55:53 +0000 Received: from twspam01.aspeedtech.com ([211.20.114.71]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqP0f-005R08-9Y for linux-arm-kernel@lists.infradead.org; Mon, 16 May 2022 00:54:57 +0000 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 24G0eWss022582; Mon, 16 May 2022 08:40:32 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from Chiawei-PC03.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 16 May 2022 08:54:05 +0800 From: Chia-Wei Wang To: , , , , , , , , , , , CC: Subject: [PATCH v5 1/4] dt-bindings: aspeed: Add eSPI controller Date: Mon, 16 May 2022 08:54:09 +0800 Message-ID: <20220516005412.4844-2-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220516005412.4844-1-chiawei_wang@aspeedtech.com> References: <20220516005412.4844-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 24G0eWss022582 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220515_175453_638922_F6426C1D X-CRM114-Status: GOOD ( 12.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add dt-bindings for Aspeed eSPI controller Signed-off-by: Chia-Wei Wang --- .../devicetree/bindings/soc/aspeed/espi.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/espi.yaml diff --git a/Documentation/devicetree/bindings/soc/aspeed/espi.yaml b/Documentation/devicetree/bindings/soc/aspeed/espi.yaml new file mode 100644 index 000000000000..aa91ec8caf6a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/espi.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2021 Aspeed Technology Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/aspeed/espi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Aspeed eSPI Controller + +maintainers: + - Chia-Wei Wang + - Ryan Chen + +description: + Aspeed eSPI controller implements a slave side eSPI endpoint device + supporting the four eSPI channels, namely peripheral, virtual wire, + out-of-band, and flash. + +properties: + compatible: + items: + - enum: + - aspeed,ast2500-espi + - aspeed,ast2600-espi + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^espi-ctrl@[0-9a-f]+$": + type: object + + description: Control of the four basic eSPI channels + + properties: + compatible: + items: + - enum: + - aspeed,ast2500-espi-ctrl + - aspeed,ast2600-espi-ctrl + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + perif,memcyc-enable: + type: boolean + description: Enable memory cycle over eSPI peripheral channel + + perif,memcyc-src-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The Host side address to be decoded into the memory cycle over eSPI peripheral channel + + perif,memcyc-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The size of the memory region allocated for the memory cycle over eSPI peripheral channel + minimum: 65536 + + perif,dma-mode: + type: boolean + description: Enable DMA support for eSPI peripheral channel + + oob,dma-mode: + type: boolean + description: Enable DMA support for eSPI out-of-band channel + + oob,dma-tx-desc-num: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2 + maximum: 1023 + description: The number of TX descriptors available for eSPI OOB DMA engine + + oob,dma-rx-desc-num: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2 + maximum: 1023 + description: The number of RX descriptors available for eSPI OOB DMA engine + + flash,dma-mode: + type: boolean + description: Enable DMA support for eSPI flash channel + + flash,safs-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + default: 0 + description: Slave-Attached-Sharing-Flash mode, 0->Mix, 1->SW, 2->HW + + dependencies: + perif,memcyc-src-addr: [ "perif,memcyc-enable" ] + perif,memcyc-size: [ "perif,memcyc-enable" ] + oob,dma-tx-desc-num: [ "oob,dma-mode" ] + oob,dma-rx-desc-num: [ "oob,dma-mode" ] + + required: + - compatible + - interrupts + - clocks + + "^espi-mmbi@[0-9a-f]+$": + type: object + + description: Control of the PCH-BMC data exchange over eSPI peripheral memory cycle + + properties: + compatible: + const: aspeed,ast2600-espi-mmbi + + interrupts: + maxItems: 1 + + required: + - compatible + - interrupts + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + + espi: espi@1e6ee000 { + compatible = "aspeed,ast2600-espi", "simple-mfd", "syscon"; + reg = <0x1e6ee000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6ee000 0x1000>; + + espi_ctrl: espi-ctrl@0 { + compatible = "aspeed,ast2600-espi-ctrl"; + reg = <0x0 0x800>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>; + }; + + espi_mmbi: espi-mmbi@800 { + compatible = "aspeed,ast2600-espi-mmbi"; + reg = <0x800 0x50>; + interrupts = ; + }; + };