diff mbox series

drm/meson: add YUV422 output support

Message ID 20220516072245.10745-1-christianshewitt@gmail.com (mailing list archive)
State New, archived
Headers show
Series drm/meson: add YUV422 output support | expand

Commit Message

Christian Hewitt May 16, 2022, 7:22 a.m. UTC
From: Dongjin Kim <tobetter@gmail.com>

Support YUV422 output from the Amlogic Meson SoC VPU to the HDMI
controller. Without this YUV422 format out of the HDMI encoder
leads to using the dw-hdmi YUV444 to YUV422 color conversion which
gives wrong colors and a green line on the left edge of the screen.

Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Furkan Kardame <f.kardame@manjaro.org>
---
I've had this patch in my sources for some time now; originally picked
from Dongjin's mainline branches for Hardkernel boards and tweaked for
some minor renaming after DRM bridge changes were merged. Furkhan has
reminded me this is still needed a couple of days ago and now the same
issue is reported on the mailing list [0] so best to submit it. If a
fixes tag is required? please advise the commit and i'll resend.

 drivers/gpu/drm/meson/meson_encoder_hdmi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Neil Armstrong May 18, 2022, 7:10 a.m. UTC | #1
On 16/05/2022 09:22, Christian Hewitt wrote:
> From: Dongjin Kim <tobetter@gmail.com>
> 
> Support YUV422 output from the Amlogic Meson SoC VPU to the HDMI
> controller. Without this YUV422 format out of the HDMI encoder
> leads to using the dw-hdmi YUV444 to YUV422 color conversion which
> gives wrong colors and a green line on the left edge of the screen.
> 
> Signed-off-by: Dongjin Kim <tobetter@gmail.com>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> Tested-by: Furkan Kardame <f.kardame@manjaro.org>
> ---
> I've had this patch in my sources for some time now; originally picked
> from Dongjin's mainline branches for Hardkernel boards and tweaked for
> some minor renaming after DRM bridge changes were merged. Furkhan has
> reminded me this is still needed a couple of days ago and now the same
> issue is reported on the mailing list [0] so best to submit it. If a
> fixes tag is required? please advise the commit and i'll resend.
> 
>   drivers/gpu/drm/meson/meson_encoder_hdmi.c | 8 +++++++-
>   1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> index 5e306de6f485..08529efb4405 100644
> --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
> @@ -218,7 +218,8 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge,
>   	if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) {
>   		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
>   		yuv420_mode = true;
> -	}
> +	} else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
> +		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
>   
>   	/* VENC + VENC-DVI Mode setup */
>   	meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode);
> @@ -230,6 +231,10 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge,
>   		/* Setup YUV420 to HDMI-TX, no 10bit diphering */
>   		writel_relaxed(2 | (2 << 2),
>   			       priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
> +	else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
> +		/* Setup YUV422 to HDMI-TX, no 10bit diphering */
> +		writel_relaxed(1 | (2 << 2),
> +				priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
>   	else
>   		/* Setup YUV444 to HDMI-TX, no 10bit diphering */
>   		writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
> @@ -257,6 +262,7 @@ static void meson_encoder_hdmi_atomic_disable(struct drm_bridge *bridge,
>   
>   static const u32 meson_encoder_hdmi_out_bus_fmts[] = {
>   	MEDIA_BUS_FMT_YUV8_1X24,
> +	MEDIA_BUS_FMT_UYVY8_1X16,
>   	MEDIA_BUS_FMT_UYYVYY8_0_5X24,
>   };
>   

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong May 18, 2022, 7:23 a.m. UTC | #2
Hi,

On Mon, 16 May 2022 07:22:45 +0000, Christian Hewitt wrote:
> From: Dongjin Kim <tobetter@gmail.com>
> 
> Support YUV422 output from the Amlogic Meson SoC VPU to the HDMI
> controller. Without this YUV422 format out of the HDMI encoder
> leads to using the dw-hdmi YUV444 to YUV422 color conversion which
> gives wrong colors and a green line on the left edge of the screen.
> 
> [...]

Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-next)

[1/1] drm/meson: add YUV422 output support
      https://cgit.freedesktop.org/drm/drm-misc/commit/?id=c193a003dc46ae601f46908b41d6f485b87db1ad
diff mbox series

Patch

diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
index 5e306de6f485..08529efb4405 100644
--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
@@ -218,7 +218,8 @@  static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge,
 	if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) {
 		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
 		yuv420_mode = true;
-	}
+	} else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
+		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
 
 	/* VENC + VENC-DVI Mode setup */
 	meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode);
@@ -230,6 +231,10 @@  static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge,
 		/* Setup YUV420 to HDMI-TX, no 10bit diphering */
 		writel_relaxed(2 | (2 << 2),
 			       priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
+	else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
+		/* Setup YUV422 to HDMI-TX, no 10bit diphering */
+		writel_relaxed(1 | (2 << 2),
+				priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
 	else
 		/* Setup YUV444 to HDMI-TX, no 10bit diphering */
 		writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
@@ -257,6 +262,7 @@  static void meson_encoder_hdmi_atomic_disable(struct drm_bridge *bridge,
 
 static const u32 meson_encoder_hdmi_out_bus_fmts[] = {
 	MEDIA_BUS_FMT_YUV8_1X24,
+	MEDIA_BUS_FMT_UYVY8_1X16,
 	MEDIA_BUS_FMT_UYYVYY8_0_5X24,
 };