diff mbox series

[v1,1/9] arm64/sysreg: Generate definitions for CCSIDR2_EL1

Message ID 20220517182219.2171814-2-broonie@kernel.org (mailing list archive)
State New, archived
Headers show
Series arm64/sysreg: More system register generation | expand

Commit Message

Mark Brown May 17, 2022, 6:22 p.m. UTC
Convert CCSIDR2_EL1 to be automatically generated as per DDI0487H.a. No
functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 1 -
 arch/arm64/tools/sysreg         | 8 ++++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

Comments

Mark Rutland May 20, 2022, 2:53 p.m. UTC | #1
On Tue, May 17, 2022 at 07:22:11PM +0100, Mark Brown wrote:
> Convert CCSIDR2_EL1 to be automatically generated as per DDI0487H.a. No
> functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>

The commit message and title say CCSIDR2_EL1, but the patch changes CCSIDR_EL1
(no '2').

> ---
>  arch/arm64/include/asm/sysreg.h | 1 -
>  arch/arm64/tools/sysreg         | 8 ++++++++
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 91e4f8601393..45d29f34d9b3 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -456,7 +456,6 @@
>  
>  #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
>  
> -#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
>  #define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
>  #define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)
>  #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index a236d7a821b4..db395dabc9e9 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -212,6 +212,14 @@ Sysreg	SMCR_EL1	3	0	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg
>  
> +Sysreg	CCSIDR_EL1	3	1	0	0	0
> +Res0	63:56
> +Field	55:32	NumSets
> +Res0	31:24
> +Field	23:3	Associativity
> +Field	2:0	LineSize
> +EndSysreg

Looking at ARM DDI 0487H.a pages D13-5299 to D13-5301, the layout of CCSIDR_EL1
depends on whether FEAT_CCIDX is implemented:

* When FEAT_CCIDX is implemented:
  63:56 RES0
  55:32 NumSets
  31:24 RES0
  23:3  Associativity
  2:0   LineSize

* When FEAT_CCIDX is not implemented (e.g. baseline ARMv8.0)
  63:32 RES0
  31:28 UNKNOWN
  27:13 NumSets
  12:3  Associativity
  2:0   LineSize

The existing code doesn't depend upn the layout, so I agree there's no
functional change.

However, since this patch adds the FEAT_CCIDX layout specifically, I reckon we
need to think about how to capture that fact in the naming.

Thanks,
Mark.

> +
>  Sysreg	SMIDR_EL1	3	1	0	0	6
>  Res0	63:32
>  Field	31:24	IMPLEMENTER
> -- 
> 2.30.2
>
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 91e4f8601393..45d29f34d9b3 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -456,7 +456,6 @@ 
 
 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
 
-#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
 #define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
 #define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)
 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a236d7a821b4..db395dabc9e9 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -212,6 +212,14 @@  Sysreg	SMCR_EL1	3	0	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+Sysreg	CCSIDR_EL1	3	1	0	0	0
+Res0	63:56
+Field	55:32	NumSets
+Res0	31:24
+Field	23:3	Associativity
+Field	2:0	LineSize
+EndSysreg
+
 Sysreg	SMIDR_EL1	3	1	0	0	6
 Res0	63:32
 Field	31:24	IMPLEMENTER