diff mbox series

[v1,3/9] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx

Message ID 20220517182219.2171814-4-broonie@kernel.org (mailing list archive)
State New, archived
Headers show
Series arm64/sysreg: More system register generation | expand

Commit Message

Mark Brown May 17, 2022, 6:22 p.m. UTC
Convert the various CONTEXTIDR_ELx register definitions to be automatically
generated following the definitions in DDI0487H.a. No functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h |  2 --
 arch/arm64/tools/sysreg         | 21 +++++++++++++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

Comments

Mark Rutland May 20, 2022, 3:01 p.m. UTC | #1
On Tue, May 17, 2022 at 07:22:13PM +0100, Mark Brown wrote:
> Convert the various CONTEXTIDR_ELx register definitions to be automatically
> generated following the definitions in DDI0487H.a. No functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h |  2 --
>  arch/arm64/tools/sysreg         | 21 +++++++++++++++++++++
>  2 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index d7a98dc62029..5a5d6bdaa806 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -449,7 +449,6 @@
>  #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
>  #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
>  
> -#define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
>  #define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
>  
>  #define SYS_SCXTNUM_EL1			sys_reg(3, 0, 13, 0, 7)
> @@ -628,7 +627,6 @@
>  #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
>  #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
>  #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
> -#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
>  #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
>  #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
>  #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 8b5788cbf099..e938d1117d36 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -212,6 +212,15 @@ Sysreg	SMCR_EL1	3	0	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg
>  
> +SysregFields	CONTEXTIDR_ELx
> +Res0	63:32
> +Field	31:0	PROCID
> +EndSysregFields
> +
> +Sysreg	CONTEXTIDR_EL1	3	0	13	0	1
> +Fields	CONTEXTIDR_ELx
> +EndSysreg
> +
>  Sysreg	CCSIDR_EL1	3	1	0	0	0
>  Res0	63:56
>  Field	55:32	NumSets
> @@ -278,6 +287,14 @@ Sysreg	SMCR_EL2	3	4	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg
>  
> +Sysreg	CONTEXTIDR_EL2	3	4	13	0	1
> +Fields	CONTEXTIDR_ELx
> +EndSysreg
> +
> +Sysreg	CPACR_EL12	3	5	1	0	2
> +Fields	CPACR_ELx
> +EndSysreg

Accidental addition?

> +
>  Sysreg	ZCR_EL12	3	5	1	2	0
>  Fields	ZCR_ELx
>  EndSysreg
> @@ -286,6 +303,10 @@ Sysreg	SMCR_EL12	3	5	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg
>  
> +Sysreg	CONTEXTIDR_EL12	3	5	13	0	1
> +Fields	CONTEXTIDR_ELx
> +EndSysreg

All the CONTEXTIDR_ELx bits look correct, per ARM DDI 0487H.a.

With the CPACR_EL12 definition removed:

  Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.


> +
>  SysregFields TTBRx_EL1
>  Field	63:48	ASID
>  Field	47:1	BADDR
> -- 
> 2.30.2
>
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d7a98dc62029..5a5d6bdaa806 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -449,7 +449,6 @@ 
 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
 
-#define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
 #define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
 
 #define SYS_SCXTNUM_EL1			sys_reg(3, 0, 13, 0, 7)
@@ -628,7 +627,6 @@ 
 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
-#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8b5788cbf099..e938d1117d36 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -212,6 +212,15 @@  Sysreg	SMCR_EL1	3	0	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+SysregFields	CONTEXTIDR_ELx
+Res0	63:32
+Field	31:0	PROCID
+EndSysregFields
+
+Sysreg	CONTEXTIDR_EL1	3	0	13	0	1
+Fields	CONTEXTIDR_ELx
+EndSysreg
+
 Sysreg	CCSIDR_EL1	3	1	0	0	0
 Res0	63:56
 Field	55:32	NumSets
@@ -278,6 +287,14 @@  Sysreg	SMCR_EL2	3	4	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+Sysreg	CONTEXTIDR_EL2	3	4	13	0	1
+Fields	CONTEXTIDR_ELx
+EndSysreg
+
+Sysreg	CPACR_EL12	3	5	1	0	2
+Fields	CPACR_ELx
+EndSysreg
+
 Sysreg	ZCR_EL12	3	5	1	2	0
 Fields	ZCR_ELx
 EndSysreg
@@ -286,6 +303,10 @@  Sysreg	SMCR_EL12	3	5	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+Sysreg	CONTEXTIDR_EL12	3	5	13	0	1
+Fields	CONTEXTIDR_ELx
+EndSysreg
+
 SysregFields TTBRx_EL1
 Field	63:48	ASID
 Field	47:1	BADDR