From patchwork Thu May 19 13:56:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 12855257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44F36C433EF for ; Thu, 19 May 2022 15:02:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3YPgpOITi1TnZmgLuTDntt+w7xhHe3Ti5YWwACJqukY=; b=E6+4/iBWIIuzVX 8hC7+5nHQjB2HlDZKUn5mf5vKhfT4XZhWVobx1FHxbKsGvpzeuyNg4tUQ2mlA0+fket14ObRshpzY YbFiLM1fvC8b8ZNWHHio96WMwgq5Il+U+ThwxnMpoChohA6n5CSC2dnVHlip3ffmuGXNcpiUG0uL5 EufIuHB26UZWR97WaYCIwhuxKVOji9CnQBtxrSt4YBnu2wvUXh+21qm1UvdcXiMCgr5kgZlqgUFlN c3GAdz1YDOpj95YtozIxbR7skwQQawcUcM99Ih6126X7iJx+uj3VyYLYq73E0ZMCX+ncVc33cMafk GApq5/rOdvwnTR4mp+FQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrheJ-007g2o-2W; Thu, 19 May 2022 15:01:12 +0000 Received: from relay1-d.mail.gandi.net ([2001:4b98:dc4:8::221]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrgeB-007BYP-5K for linux-arm-kernel@lists.infradead.org; Thu, 19 May 2022 13:57:03 +0000 Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id C27B9240018; Thu, 19 May 2022 13:56:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1652968616; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+OOpYFAzojc6pPu7a3Cjy9JL3eWpwDvEMOqBp/XLQgg=; b=dtLrrAdyCTFWwrLJm+qeQJGHpa3bmwxvW+UgOFJ2YIIByrWEe4gUjtmZGjssJ89W9srh8R kZUUlf/rHIlPTNDYwmaIVUZU1WPsbHJKInceDUATxGClPhC6AZXeJcAej8dgHMEoW0dq0E lYbranHyebS2g9nlHnKF1ZapApg5OPpr1GWEzmXkkxa2ZFeR2fqPG0GDXmowXSFxd5lFX/ 9e+Cg0cVQKmps3VHV4/wykA4TXYwrxEHWkfwDBp3Ybo7yQf2RO+YN26CKmh0edA2YauRGK dissJ8wdsdBTMbsA9chamCqVZRRQVvWCNiKLkCb7FvfgSTYn5wUCMwwP0sgdkA== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Richard Cochran , Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com Subject: [PATCH net-next 1/6] net: phy: Introduce QUSGMII PHY mode Date: Thu, 19 May 2022 15:56:42 +0200 Message-Id: <20220519135647.465653-2-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220519135647.465653-1-maxime.chevallier@bootlin.com> References: <20220519135647.465653-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220519_065659_923141_48C9E351 X-CRM114-Status: GOOD ( 15.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The QUSGMII mode is a derivative of Cisco's USXGMII standard. This standard is pretty similar to SGMII, but allows for faster speeds, and has the build-in bits for Quad and Octa variants (like QSGMII). The main difference with SGMII/QSGMII is that USXGMII/QUSGMII re-uses the preamble to carry various information, named 'Extensions'. As of today, the USXGMII standard only mentions the "PCH" extension, which is used to convey timestamps, allowing in-band signaling of PTP timestamps without having to modify the frame itself. This commit adds support for that mode. When no extension is in use, it behaves exactly like QSGMII, although it's not compatible with QSGMII. Signed-off-by: Maxime Chevallier --- Documentation/networking/phy.rst | 9 +++++++++ drivers/net/phy/phylink.c | 3 +++ include/linux/phy.h | 3 +++ 3 files changed, 15 insertions(+) diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index d43da709bf40..72c3c9fbce6f 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -308,6 +308,15 @@ Some of the interface modes are described below: rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying data rate of 100Mpbs. +``PHY_INTERFACE_MODE_QUSGMII`` + This defines the Cisco the Quad USGMII mode, which is the Quad variant of + the USGMII (Universal SGMII) link. It's very similar to QSGMII, but uses + a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not + only the port id, but also so-called "extensions". The only documented + extension so-far in the specification is the inclusion of timestamps, for + PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the + same capabilities in terms of link speed and negociation. + Pause frames / flow control =========================== diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 06943889d747..228eed5bc85a 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -320,6 +320,7 @@ void phylink_get_linkmodes(unsigned long *linkmodes, phy_interface_t interface, case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_GMII: caps |= MAC_1000HD | MAC_1000FD; @@ -631,6 +632,7 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode) switch (pl->link_config.interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: phylink_set(pl->supported, 10baseT_Half); phylink_set(pl->supported, 10baseT_Full); phylink_set(pl->supported, 100baseT_Half); @@ -2944,6 +2946,7 @@ void phylink_mii_c22_pcs_decode_state(struct phylink_link_state *state, case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: phylink_decode_sgmii_word(state, lpa); break; diff --git a/include/linux/phy.h b/include/linux/phy.h index 36ca2b5c2253..4a2731c78590 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -152,6 +152,7 @@ typedef enum { PHY_INTERFACE_MODE_USXGMII, /* 10GBASE-KR - with Clause 73 AN */ PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -267,6 +268,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "10gbase-kr"; case PHY_INTERFACE_MODE_100BASEX: return "100base-x"; + case PHY_INTERFACE_MODE_QUSGMII: + return "qusgmii"; default: return "unknown"; }