From patchwork Fri May 20 03:15:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kefeng Wang X-Patchwork-Id: 12856246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CAA2BC433F5 for ; Fri, 20 May 2022 03:06:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=T8hAp05/OcQ1YI8dPzPw7n/7o0OKAQF1lqr4Ow3F/aU=; b=swcupJTMltWWHd u8g4v9+n+8E/xn/hGwaJWLvJvUg9m4SNBxgtREo/mDXAQV+k2NAEqRsSa2JGTGAqr64hpfP8Gq4i2 L7H0WYMQm2sxq7m7lOUJevbJ8F1Y0zKdArlQLcY3UF3PLpOZKf1Veqw3dWz8HKZRbn4UCkLP2FDLM f3i9ocRPOXMH7qKzbipgSgoRpyCI6r9B2yDhaUUBdw3grwwvyTv7wBNZZFMlJ1z7XVA2ZPzVaFKla OGIeA1/00SrNpX+DOaL2Ar8Cw+4dQnmMU0VQNjnf1DW/pfIf/BCSts/FYPktmWMXqHl399fH++AAS +vIrpNE4aXxgqZot9HfA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrsxJ-00ACJv-Ss; Fri, 20 May 2022 03:05:33 +0000 Received: from szxga08-in.huawei.com ([45.249.212.255]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrsx7-00ACFe-Em for linux-arm-kernel@lists.infradead.org; Fri, 20 May 2022 03:05:24 +0000 Received: from dggpemm500021.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4L4BPz0vfxz1JCQW; Fri, 20 May 2022 11:03:51 +0800 (CST) Received: from dggpemm500001.china.huawei.com (7.185.36.107) by dggpemm500021.china.huawei.com (7.185.36.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 20 May 2022 11:05:14 +0800 Received: from localhost.localdomain.localdomain (10.175.113.25) by dggpemm500001.china.huawei.com (7.185.36.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 20 May 2022 11:05:14 +0800 From: Kefeng Wang To: , , , , , , Jonathan Corbet CC: , Kefeng Wang Subject: [PATCH v2 1/2] Documentation/barriers: Add memory barrier dma_mb() Date: Fri, 20 May 2022 11:15:47 +0800 Message-ID: <20220520031548.175582-2-wangkefeng.wang@huawei.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220520031548.175582-1-wangkefeng.wang@huawei.com> References: <20220520031548.175582-1-wangkefeng.wang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.113.25] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggpemm500001.china.huawei.com (7.185.36.107) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220519_200521_701792_CE93CCC4 X-CRM114-Status: GOOD ( 12.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The memory barrier dma_mb() is introduced by commit a76a37777f2c ("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer"), which is used to ensure that prior (both reads and writes) accesses to memory by a CPU are ordered w.r.t. a subsequent MMIO write. Signed-off-by: Kefeng Wang --- Documentation/memory-barriers.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index b12df9137e1c..1eabcc0e4eca 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -1894,10 +1894,13 @@ There are some more advanced barrier functions: (*) dma_wmb(); (*) dma_rmb(); + (*) dma_mb(); These are for use with consistent memory to guarantee the ordering of writes or reads of shared memory accessible to both the CPU and a - DMA capable device. + DMA capable device, in the case of ensure the prior (both reads and + writes) accesses to memory by a CPU are ordered w.r.t. a subsequent + MMIO write, dma_mb(). For example, consider a device driver that shares memory with a device and uses a descriptor status value to indicate if the descriptor belongs