From patchwork Mon May 23 06:00:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12858666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 849A5C433EF for ; Mon, 23 May 2022 09:32:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PzcwBcRhwN7AnuaGJNtv92wbVmsw1gy0NCd0bSrOr3M=; b=t3EDQmokEgmI0i fivUb4YzkpYSOD7rjk9wNmORDKgVL/WL3DCSSXJLGose/qV5YjLLxS8p1Zcbchzt2FIj/hriJpGGG 6nPBTejFRnu+WjIygopqfkEsy3x1UsNsOJZM9XRWtlFQZGnHrwbCp+BrN+zLw7O87y1hmtiswStEB SM/QsmyXNNd75n6LwqqB4M2D2Xa+RupGTItHIKp7vMWmMowqJBPRTmdcWOxsQzC5iKy1VBO3haSFk hh+n6ruz180EYqKrAw4jON34TYBNl/sNmTNtAhKStyrSy1yGm2iWEl0ACjSEx+g6tLDj8OUixt0ZI GpVfOyEY0Fled8QSCk/A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt4PD-002rTm-9m; Mon, 23 May 2022 09:31:15 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt2oh-002A7b-BZ; Mon, 23 May 2022 07:49:27 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=xcHrYZLXLPlRTq+0vnlhR2b9fxEyAoum33HaLYazOCw=; b=YajXRZDRE8bvZfaWdtjz9BkF6/ 48zLsti+/OQn6N/L0uRjnAwDLZ0YONydwN8eE5YMdWPCubh9ziQFTkJE3/E38SHnuE7S3Yj8bmMsI DUDAIZqhC0RuQlVkKpQaW4kNEEIlIsi2McHdMHA2ftEEYf/Of/O5RU9mYVSm1R0Wdn4C0OC9a2F1f iCin51lnXnT1yTzGMmNLcoK7JWAQZd+OJS/MQErUnXZEvHUmc8QPjgIYEeU5QKSbAxeFETayHmXI0 0ffi+jzZeA3CYs8RJRxr0s7+n9gOD+BRP56WO4mo8niXXAtAovu596DSSGKXruAHxQ3zlxWBlMTRC vPeINmtA==; Received: from mailgw01.mediatek.com ([216.200.240.184]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt1C0-000snx-73; Mon, 23 May 2022 06:05:30 +0000 X-UUID: c4f9bbe7d34b4ed4855c88f19526191b-20220522 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:2f0c01be-0fdf-43ae-bd9a-3c2b4788707a, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09, CLOUDID:aca73e7a-5ef6-470b-96c9-bdb8ced32786, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: c4f9bbe7d34b4ed4855c88f19526191b-20220522 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1333652929; Sun, 22 May 2022 23:04:56 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 22 May 2022 23:01:00 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 23 May 2022 14:00:59 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 23 May 2022 14:00:59 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v8 12/19] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Date: Mon, 23 May 2022 14:00:49 +0800 Message-ID: <20220523060056.24396-13-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220523060056.24396-1-rex-bc.chen@mediatek.com> References: <20220523060056.24396-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_070527_531354_49FE60CE X-CRM114-Status: UNSURE ( 8.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We will use the infra_ao reset which is defined in mt8192-sys-clock and mt8195-sys-clock. The value of reset-cells is 1. Signed-off-by: Rex-BC Chen Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: NĂ­colas F. R. A. Prado Tested-by: NĂ­colas F. R. A. Prado --- .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml | 3 +++ .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml | 3 +++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml index 5705bcf1fe47..27f79175c678 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml @@ -29,6 +29,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml index 57a1503d95fe..95b6bdf99936 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml @@ -37,6 +37,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg