From patchwork Mon May 23 09:33:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12858865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03145C433EF for ; Mon, 23 May 2022 11:00:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=llUwpe+ff5alMiciMLV0GWNVmaD7TQqBHFaTo5ImUqA=; b=YQRwt8DG+c8FXE tbjzmI21YS+TuiXBpxyvyEDbldCPTMPoC5MpTGrKFXsIZF0UWr7oTxWZD5zXN61uwU+soR7jds4C3 nZE4rre2zE2EFU/STaSy8p6/cxEl1V38E1I94yvs2jEFvyDTjCtqmA4PZkRPlsDTPFvda7O0ysbt7 AOtdTw65lAG/20RFkSZx91UbUYSXRWdT6g6yFfiTu2oiL7MzF4RA6CCTlux8Ol0dHQFALvmtAn0rd s5SvAyrH1Ook9YsGF+jZdQmXkKUQ6QiPEmWWr+G+UKRUL0tP1+6jNKpf9GRdyt6IilmtKfrk/S5zB CM0LImENgH0tKDJE893w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt5ls-003TaU-7Z; Mon, 23 May 2022 10:58:44 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt4bX-002wTe-0q; Mon, 23 May 2022 09:44:05 +0000 X-UUID: 9d7e530cfc1e45dab91b2d39edfc8165-20220523 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:1f0a3b7e-0947-447a-a151-487c9486a3e8, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09, CLOUDID:3f6738e3-edbf-4bd4-8a34-dfc5f7bb086d, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:1,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 9d7e530cfc1e45dab91b2d39edfc8165-20220523 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 440772454; Mon, 23 May 2022 02:43:52 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 23 May 2022 02:33:52 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 23 May 2022 17:33:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 23 May 2022 17:33:50 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [RESEND v8 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Date: Mon, 23 May 2022 17:33:43 +0800 Message-ID: <20220523093346.28493-17-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220523093346.28493-1-rex-bc.chen@mediatek.com> References: <20220523093346.28493-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_024359_156883_7106C312 X-CRM114-Status: GOOD ( 10.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We will use mediatek clock reset as infracfg_ao reset instead of ti-syscon. To support this, remove property of ti reset and add property of #reset-cells for mediatek clock reset. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index b57e620c2c72..db16eba9d475 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,7 +10,6 @@ #include #include #include -#include / { compatible = "mediatek,mt8195"; @@ -292,20 +291,10 @@ }; infracfg_ao: syscon@10001000 { - compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; + compatible = "mediatek,mt8195-infracfg_ao", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; - - infracfg_rst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = < - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ - >; - }; + #reset-cells = <1>; }; pericfg: syscon@10003000 {