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Mon, 23 May 2022 06:45:40 -0700 Received: from [10.140.6.60] (port=57798 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nt8NQ-000GwK-4Q; Mon, 23 May 2022 06:45:40 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , CC: Rob Herring Subject: [PATCH v2 2/3] fpga: region: Add fpga-region 'power-domains' property Date: Mon, 23 May 2022 19:15:16 +0530 Message-ID: <20220523134517.4056873-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220523134517.4056873-1-nava.manne@xilinx.com> References: <20220523134517.4056873-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b8a696ac-533b-47b4-3f80-08da3cc288eb X-MS-TrafficTypeDiagnostic: CO6PR02MB7508:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0Gg9bY6QPxRoJKhsWmwcDeEOjBXVuIUfs7Gac31f1nudr+/weIoi0HdfKxV7VtIRkbSlL3yXVx1qyNKRYPl29iDsbsH/2a9ooAwk83KD644ncgvXbTerUE0SKWZc4glhBEmMIPyV/XkXT3kBNwgIybqlof/QBlIt4gwo3ZcFkcUgPWyYbhEvArWHOeWV63uWTmY+/KxJJFL7oea+VtzrKmocH7nmfU1UPraKtlWGd634u++f/c2o0p4jPzxmWx2IKirv3zvkVWsm3JlvLPM234xdKGjYHbxTbrr/8A8dc8ETJ2x50a4qVTC4UMOAP+1rSX+3b52lvg+qcgXCGE7OMbaLaiAGfgjJ9q71QqnO74ocOYt/YyfxdXe1oPqp+zdtOIH630YcIWGAUYRiAQNqaPUwwpIpQ4InkXQZ59g8NOKG/sxTmwtd+Vw0N+mSTwP8Jz+hm6ysaDbMRrvAwt2K1MoapmrJz0IMjyUBY4VXjalXvnQe4GS9dJ5kdc2BvfrVfbhyoHA8lRcfeFdRQg5RzQRPwpkQM+wjDKB3hnVVdhnNUuBTovrE11OACyLAzb9Fjis8mzrVI4qc84IJNSVXoaeLzPYlELRF2LUFZviGSaTP0u7PbfZFhVirNCLd5e0Yns8o5d5AD2epCLD+6cHDuoC2FY/TViUQKpnRlz11KJhMjA2r0QevCBc5thlJwAxlGDrS2STCWf48wbQMofJNBMPEG7Hi5iZANLZU49B7I2j1fl4NrGpQ87w1Cy5VbnIBgslqRfum3BohISL6/MKjeQ== X-Forefront-Antispam-Report: CIP:149.199.62.198; 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Signed-off-by: Nava kishore Manne Acked-by: Rob Herring --- Changes for v2: - Updated power-domains description. .../devicetree/bindings/fpga/fpga-region.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index 7d3515264838..f299c3749505 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -196,6 +196,20 @@ Optional properties: - config-complete-timeout-us : The maximum time in microseconds time for the FPGA to go to operating mode after the region has been programmed. - child nodes : devices in the FPGA after programming. +- power-domains : A phandle and power domain specifier pair to the power domain + which is responsible for turning on/off the power to the FPGA/PL region. +Example: + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&zynqmp_pcap>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&zynqmp_firmware PL_PD>; + }; + + The PL_PD power domain will be turned on before loading the bitstream +and turned off while removing/unloading the bitstream using overlays. In the example below, when an overlay is applied targeting fpga-region0, fpga_mgr is used to program the FPGA. Two bridges are controlled during