From patchwork Wed May 25 01:31:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 12860645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C601C433EF for ; Wed, 25 May 2022 01:34:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=C3RHJ4OzOOeaIv77uX0k2U1x06UsaEzWJlPGgRlb4kc=; b=bxcC6KV00uxEi/ AGR8268AIliPG8T63Ni6oX+Ri0Jz4bgcK1TTM6JFSNQtNHbd7h6Z34fBxpj9UX9wQPo2M+dN/lqml Elzb9aoc3E847Dm5H4DdJK99/gq3tW02Q5fl+vtnpTYxE9SlpDAoeXLABgnpHfSFCdpV2mReP5Rjw L0PLBL3FUzrtyGpmFkE9vpdFe7THfGtdO36qt6YqxOuiqTK2V+WYY0rMkie110eOeajmASh57TYyh pFadkJ6VpmabeVdRGPSd/sVge2yE/GDVu2nW0tJM+JX4PZ14shmkhzRllOnMJ8v85ttaoYueqgFZ4 FuxkawNpg0qZ8KOgaE3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ntftL-009bIS-8b; Wed, 25 May 2022 01:32:51 +0000 Received: from mo-csw1116.securemx.jp ([210.130.202.158] helo=mo-csw.securemx.jp) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ntfsz-009bE6-Jm for linux-arm-kernel@lists.infradead.org; Wed, 25 May 2022 01:32:33 +0000 Received: by mo-csw.securemx.jp (mx-mo-csw1116) id 24P1W79U014816; Wed, 25 May 2022 10:32:07 +0900 X-Iguazu-Qid: 2wHHoRQqLZjpEs969Y X-Iguazu-QSIG: v=2; s=0; t=1653442327; q=2wHHoRQqLZjpEs969Y; m=Xr7wfXU0P28tQrglBFUkXafUeWb8aRJHHN/nDBBqDyc= Received: from imx12-a.toshiba.co.jp (imx12-a.toshiba.co.jp [61.202.160.135]) by relay.securemx.jp (mx-mr1110) id 24P1W605016226 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Wed, 25 May 2022 10:32:06 +0900 From: Nobuhiro Iwamatsu To: Joerg Roedel , Will Deacon , Rob Herring Cc: yuji2.ishikawa@toshiba.co.jp, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Nobuhiro Iwamatsu Subject: [PATCH 2/3] iommu: bindings: Add binding documentation for Toshiba Visconti5 IOMMU device Date: Wed, 25 May 2022 10:31:46 +0900 X-TSB-HOP2: ON Message-Id: <20220525013147.2215355-3-nobuhiro1.iwamatsu@toshiba.co.jp> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220525013147.2215355-1-nobuhiro1.iwamatsu@toshiba.co.jp> References: <20220525013147.2215355-1-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220524_183230_015302_CDB2DD2F X-CRM114-Status: GOOD ( 11.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add documentation for the binding of Toshiba Visconti5 SoC's IOMMU. Signed-off-by: Nobuhiro Iwamatsu --- .../bindings/iommu/toshiba,visconti-atu.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml diff --git a/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml b/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml new file mode 100644 index 000000000000..af8d6688fa70 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/toshiba,visconti-atu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba ARM SoC Visconti5 IOMMU (ATU) + +maintainers: + - Nobuhiro Iwamatsu + +description: |+ + IOMMU (ATU) driver can bse used for Visconti5's multimedia IPs, such as + DCNN (Deep Convolutional Neural Network), VIIF(Video Input), VOIF(Video + output), and others. + +properties: + compatible: + const: toshiba,visconti-atu + + reg: + maxItems: 1 + + "#iommu-cells": + const: 0 + + toshiba,max-entry: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The size of entry for address + enum: + - 16 + - 32 + + toshiba,reserved-entry: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The reserve number of entry address. + default: 0 + minimum: 0 + maximum: 32 + +required: + - compatible + - reg + - "#iommu-cells" + - toshiba,max-entry + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + atu_affine0: iommu@1400f000 { + compatible = "toshiba,visconti-atu"; + reg = <0 0x1400F000 0 0x1000>; + toshiba,max-entry = <16>; + toshiba,reserved-entry = <1>; + #iommu-cells = <0>; + }; + };