| Message ID | 20220602141151.3431212-1-wen.ping.teh@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] arm64: dts: Add support for Stratix 10 Software Virtual Platform | expand |
On 02/06/2022 16:11, wen.ping.teh@intel.com wrote: > From: Teh Wen Ping <wen.ping.teh@intel.com> > > Add Stratix 10 Software Virtual Platform device tree > > Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com> > --- > > changes in v2: > -remove indentation before GPL > -change root compatible to "altr,socfpga-stratix10" > -remove bootargs > -move clock-frequency to label > -remove l2-cache > -remove no longer exist authors from commit message > > arch/arm64/Kconfig.platforms | 3 +- > arch/arm64/boot/dts/altera/Makefile | 3 +- > .../dts/altera/socfpga_stratix10_swvp.dts | 117 ++++++++++++++++++ > 3 files changed, 121 insertions(+), 2 deletions(-) > create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index de9a18d3026f..48abe5dafaae 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -249,7 +249,8 @@ config ARCH_INTEL_SOCFPGA > bool "Intel's SoCFPGA ARMv8 Families" > help > This enables support for Intel's SoCFPGA ARMv8 families: > - Stratix 10 (ex. Altera), Agilex and eASIC N5X. > + Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, > + Agilex and eASIC N5X. > > config ARCH_SYNQUACER > bool "Socionext SynQuacer SoC Family" > diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile > index 4db83fbeb115..1bf0c472f6b4 100644 > --- a/arch/arm64/boot/dts/altera/Makefile > +++ b/arch/arm64/boot/dts/altera/Makefile > @@ -1,3 +1,4 @@ > # SPDX-License-Identifier: GPL-2.0-only > dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ > - socfpga_stratix10_socdk_nand.dtb > + socfpga_stratix10_socdk_nand.dtb \ > + socfpga_stratix10_swvp.dtb > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts > new file mode 100644 > index 000000000000..93fa5091a6c3 > --- /dev/null > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts > @@ -0,0 +1,117 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2022, Intel Corporation > + */ > + > +#include "socfpga_stratix10.dtsi" > + > +/ { > + model = "SOCFPGA Stratix 10 SWVP"; > + compatible = "altr,socfpga-stratix10"; You cannot use someone else's compatible. You need your own and then also you need to document it. Check existing sources for examples. Documentation/devicetree/bindings/arm/altera.yaml > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + > + timer0 = &timer0; > + timer1 = &timer1; > + timer2 = &timer2; > + timer3 = &timer3; > + > + ethernet0 = &gmac0; > + ethernet1 = &gmac1; > + ethernet2 = &gmac2; > + }; > + > + chosen { > + stdout-path = "serial1:115200n8"; > + linux,initrd-start = <0x10000000>; > + linux,initrd-end = <0x125c8324>; Best regards, Krzysztof
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index de9a18d3026f..48abe5dafaae 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -249,7 +249,8 @@ config ARCH_INTEL_SOCFPGA bool "Intel's SoCFPGA ARMv8 Families" help This enables support for Intel's SoCFPGA ARMv8 families: - Stratix 10 (ex. Altera), Agilex and eASIC N5X. + Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, + Agilex and eASIC N5X. config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile index 4db83fbeb115..1bf0c472f6b4 100644 --- a/arch/arm64/boot/dts/altera/Makefile +++ b/arch/arm64/boot/dts/altera/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ - socfpga_stratix10_socdk_nand.dtb + socfpga_stratix10_socdk_nand.dtb \ + socfpga_stratix10_swvp.dtb diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts new file mode 100644 index 000000000000..93fa5091a6c3 --- /dev/null +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022, Intel Corporation + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SOCFPGA Stratix 10 SWVP"; + compatible = "altr,socfpga-stratix10"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + linux,initrd-start = <0x10000000>; + linux,initrd-end = <0x125c8324>; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&cpu0 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu1 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu2 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu3 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; + snps,max-mtu = <0x0>; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&mmc { + status = "okay"; + altr,dw-mshc-ciu-div = <0x3>; + altr,dw-mshc-sdr-timing = <0x0 0x3>; + cap-sd-highspeed; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&usb1 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&rst { + altr,modrst-offset = <0x20>; +}; + +&sysmgr { + reg = <0xffd12000 0x1000>; + interrupts = <0x0 0x10 0x4>; + cpu1-start-addr = <0xffd06230>; +};