| Message ID | 20220603121802.30320-4-kavyasree.kotagiri@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for lan966x flexcom chip-select configuration | expand |
On 03.06.2022 15:18, Kavyasree Kotagiri wrote: > LAN966x SoC have 5 flexcoms. Each flexcom has 2 chip-selects. > For each chip select of each flexcom there is a configuration > register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of > configuration register is 21 because there are 21 shared pins > on each of which the chip select can be mapped. Each bit of the > register represents a different FLEXCOM_SHARED pin. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > drivers/mfd/atmel-flexcom.c | 86 ++++++++++++++++++++++++++++++++++++- > 1 file changed, 84 insertions(+), 2 deletions(-) > > diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c > index 33caa4fba6af..f87ee3606eb0 100644 > --- a/drivers/mfd/atmel-flexcom.c > +++ b/drivers/mfd/atmel-flexcom.c > @@ -28,15 +28,64 @@ > #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ > FLEX_MR_OPMODE_MASK) > > +/* LAN966x flexcom shared register offsets */ > +#define FLEX_SHRD_SS_MASK_0 0x0 > +#define FLEX_SHRD_SS_MASK_1 0x4 > +#define FLEX_SHRD_MASK 0x1FFFFF GENMASK() ? > + > +struct atmel_flex_caps { > + bool has_flx_cs; > +}; > + > struct atmel_flexcom { > - void __iomem *base; > + void __iomem *base, *flexcom_shared_base; Add a new line with: void __iomem *flexcom_shared_base; > u32 opmode; > struct clk *clk; > }; > > +static int atmel_flexcom_lan966x_cs_config(struct platform_device *pdev) > +{ > + struct atmel_flexcom *ddata = dev_get_drvdata(&pdev->dev); > + struct device_node *np = pdev->dev.of_node; > + u32 flx_shrd_pins[2], val; > + int err, i, count; > + > + count = of_property_count_u32_elems(np, "microchip,flx-shrd-pins"); > + if (count <= 0 || count > 2) { > + dev_err(&pdev->dev, "Invalid %s property (%d)\n", "flx-shrd-pins", > + count); > + return -EINVAL; > + } > + > + err = of_property_read_u32_array(np, "microchip,flx-shrd-pins", flx_shrd_pins, count); > + if (err) > + return err; > + > + for (i = 0; i < count; i++) { > + const char *flx_cs; > + > + if (flx_shrd_pins[i] > 20) Could you use a macro for 20? > + return -EINVAL; > + > + val = ~(1 << flx_shrd_pins[i]) & FLEX_SHRD_MASK; > + > + err = of_property_read_string_index(np, "microchip,flx-cs", i, &flx_cs); Wouldn't it be better to have plain u32 constants instead of strings here? > + if (err) > + return err; > + > + if (!strcmp(flx_cs, "cs0") || !strcmp(flx_cs, "cts")) > + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_0); > + else if (!strcmp(flx_cs, "cs1") || !strcmp(flx_cs, "rts")) > + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_1); I may miss something but I don't see here the approach you introduced in [1]: + err = mux_control_select(flx_mux, args.args[0]); + if (!err) { + mux_control_deselect(flx_mux); > + } > + > + return 0; > +} > + > static int atmel_flexcom_probe(struct platform_device *pdev) > { > struct device_node *np = pdev->dev.of_node; > + const struct atmel_flex_caps *caps; > struct resource *res; > struct atmel_flexcom *ddata; > int err; > @@ -76,13 +125,46 @@ static int atmel_flexcom_probe(struct platform_device *pdev) > */ > writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); > > + caps = of_device_get_match_data(&pdev->dev); > + if (!caps) { > + dev_err(&pdev->dev, "Could not retrieve flexcom caps\n"); > + return -EINVAL; As I already said on [1]: you return here but the clock remain enabled. Please take care to undo previous operations. > + } > + > + if (caps->has_flx_cs) { > + ddata->flexcom_shared_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); > + if (IS_ERR(ddata->flexcom_shared_base)) > + return dev_err_probe(&pdev->dev, > + PTR_ERR(ddata->flexcom_shared_base), > + "failed to get flexcom shared base address\n"); Ditto > + > + err = atmel_flexcom_lan966x_cs_config(pdev); > + if (err) > + return err; Ditto [1] https://lore.kernel.org/lkml/20220509084920.14529-5-kavyasree.kotagiri@microchip.com/ > + } > + > clk_disable_unprepare(ddata->clk); > > return devm_of_platform_populate(&pdev->dev); > } > > +static const struct atmel_flex_caps atmel_flexcom_caps = {}; > + > +static const struct atmel_flex_caps lan966x_flexcom_caps = { > + .has_flx_cs = true, > +}; > + > static const struct of_device_id atmel_flexcom_of_match[] = { > - { .compatible = "atmel,sama5d2-flexcom" }, > + { > + .compatible = "atmel,sama5d2-flexcom", > + .data = &atmel_flexcom_caps, > + }, > + > + { > + .compatible = "microchip,lan966x-flexcom", > + .data = &lan966x_flexcom_caps, > + }, > + > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match);
diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 33caa4fba6af..f87ee3606eb0 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -28,15 +28,64 @@ #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ FLEX_MR_OPMODE_MASK) +/* LAN966x flexcom shared register offsets */ +#define FLEX_SHRD_SS_MASK_0 0x0 +#define FLEX_SHRD_SS_MASK_1 0x4 +#define FLEX_SHRD_MASK 0x1FFFFF + +struct atmel_flex_caps { + bool has_flx_cs; +}; + struct atmel_flexcom { - void __iomem *base; + void __iomem *base, *flexcom_shared_base; u32 opmode; struct clk *clk; }; +static int atmel_flexcom_lan966x_cs_config(struct platform_device *pdev) +{ + struct atmel_flexcom *ddata = dev_get_drvdata(&pdev->dev); + struct device_node *np = pdev->dev.of_node; + u32 flx_shrd_pins[2], val; + int err, i, count; + + count = of_property_count_u32_elems(np, "microchip,flx-shrd-pins"); + if (count <= 0 || count > 2) { + dev_err(&pdev->dev, "Invalid %s property (%d)\n", "flx-shrd-pins", + count); + return -EINVAL; + } + + err = of_property_read_u32_array(np, "microchip,flx-shrd-pins", flx_shrd_pins, count); + if (err) + return err; + + for (i = 0; i < count; i++) { + const char *flx_cs; + + if (flx_shrd_pins[i] > 20) + return -EINVAL; + + val = ~(1 << flx_shrd_pins[i]) & FLEX_SHRD_MASK; + + err = of_property_read_string_index(np, "microchip,flx-cs", i, &flx_cs); + if (err) + return err; + + if (!strcmp(flx_cs, "cs0") || !strcmp(flx_cs, "cts")) + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_0); + else if (!strcmp(flx_cs, "cs1") || !strcmp(flx_cs, "rts")) + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_1); + } + + return 0; +} + static int atmel_flexcom_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + const struct atmel_flex_caps *caps; struct resource *res; struct atmel_flexcom *ddata; int err; @@ -76,13 +125,46 @@ static int atmel_flexcom_probe(struct platform_device *pdev) */ writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); + caps = of_device_get_match_data(&pdev->dev); + if (!caps) { + dev_err(&pdev->dev, "Could not retrieve flexcom caps\n"); + return -EINVAL; + } + + if (caps->has_flx_cs) { + ddata->flexcom_shared_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + if (IS_ERR(ddata->flexcom_shared_base)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ddata->flexcom_shared_base), + "failed to get flexcom shared base address\n"); + + err = atmel_flexcom_lan966x_cs_config(pdev); + if (err) + return err; + } + clk_disable_unprepare(ddata->clk); return devm_of_platform_populate(&pdev->dev); } +static const struct atmel_flex_caps atmel_flexcom_caps = {}; + +static const struct atmel_flex_caps lan966x_flexcom_caps = { + .has_flx_cs = true, +}; + static const struct of_device_id atmel_flexcom_of_match[] = { - { .compatible = "atmel,sama5d2-flexcom" }, + { + .compatible = "atmel,sama5d2-flexcom", + .data = &atmel_flexcom_caps, + }, + + { + .compatible = "microchip,lan966x-flexcom", + .data = &lan966x_flexcom_caps, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match);
LAN966x SoC have 5 flexcoms. Each flexcom has 2 chip-selects. For each chip select of each flexcom there is a configuration register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration register is 21 because there are 21 shared pins on each of which the chip select can be mapped. Each bit of the register represents a different FLEXCOM_SHARED pin. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- drivers/mfd/atmel-flexcom.c | 86 ++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 2 deletions(-)