From patchwork Tue Jun 7 13:16:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 12871911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6AE5C433EF for ; Tue, 7 Jun 2022 13:18:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Bu2UELmlrbcKw47WZDvHJeQOY7TuQ0lmcSr14IrJo8Y=; b=MwnWljjbQ18NnE rOFNjSTynQCDrD5pxDDmVAL0fTiHIgHD0R8l5NS663SlO/weefCssOwoInPNri4GMefGGAtgf5pKo 6PWASttcfwthc1WvZjxm5JBCUzKDtV10gA65QZIyVz4k3QUtJQP4QDp2e1FLhQAlVLcxUrVNAJ+8k lf/uwiQohoohJNHICCGlvB7aLPiTHxzEygSrVg9MtYi3TPWi465XV/h1JfEIHeWfpVQ12hZJuhmsP Xcc6PxggnQ8qIxxs58K2jr72wSUOHS00u0FsCOraQ6IqT+0MdJ8pSKGvWfVixMga9CqmZ40UHviqv rCHE5XJSCAJr4yqTPtSw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyZ56-007cQj-I0; Tue, 07 Jun 2022 13:17:12 +0000 Received: from forward500j.mail.yandex.net ([2a02:6b8:0:801:2::110]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyZ51-007cMx-NN; Tue, 07 Jun 2022 13:17:09 +0000 Received: from myt5-f0e8352497c8.qloud-c.yandex.net (myt5-f0e8352497c8.qloud-c.yandex.net [IPv6:2a02:6b8:c12:3c22:0:640:f0e8:3524]) by forward500j.mail.yandex.net (Yandex) with ESMTP id D93886CB6DAE; Tue, 7 Jun 2022 16:17:01 +0300 (MSK) Received: from myt6-654ec0a0ab93.qloud-c.yandex.net (myt6-654ec0a0ab93.qloud-c.yandex.net [2a02:6b8:c12:1d80:0:640:654e:c0a0]) by myt5-f0e8352497c8.qloud-c.yandex.net (mxback/Yandex) with ESMTP id 3zNxHODKJI-H0fO9MpU; Tue, 07 Jun 2022 16:17:01 +0300 X-Yandex-Fwd: 2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1654607821; bh=hQhndwkj71U3FGMLsP/eq3Nugqa3M1fyrFTWT3q68hQ=; h=In-Reply-To:References:Date:Subject:Cc:To:From:Message-Id; b=NJnzfUlSlee1UpmU5Dgch59/F8lXLuIVD8FhhXiFA9CJ1kWdMxKhcIdnWVy6AZTyV 3DqZZltYprFxT3qkivpyJ0ssDY7OpxzlKcpbiyThK37jmqOpTq4pnBxIpCpTTzdWHO q+ZchxAeidjMHg1V/WiYd32NttwLoMnkuASiG1Ls= Authentication-Results: myt5-f0e8352497c8.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by myt6-654ec0a0ab93.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id sOXgg17Zrk-GxM4mQbH; Tue, 07 Jun 2022 16:16:59 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin To: Cc: Genevieve Chan , =?utf-8?b?Sm/Do28gTcOh?= =?utf-8?b?cmlvIERvbWluZ29z?= , Nikita Shubin , Atish Patra , Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-kernel@vger.kernel.org (open list), linux-riscv@lists.infradead.org (open list:RISC-V PMU DRIVERS), linux-arm-kernel@lists.infradead.org (moderated list:ARM PMU PROFILING AND DEBUGGING), linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM) Subject: [PATCH v3 2/4] RISC-V: Support CPUID for risc-v in perf Date: Tue, 7 Jun 2022 16:16:45 +0300 Message-Id: <20220607131648.29439-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607131648.29439-1-nikita.shubin@maquefel.me> References: <20220607131648.29439-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_061708_176782_D16D8B72 X-CRM114-Status: GOOD ( 19.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: João Mário Domingos This patch creates the header.c file for the risc-v architecture and introduces support for PMU identification through sysfs. It is now possible to configure pmu-events in risc-v. Depends on patch [1], that introduces the id sysfs file. Signed-off-by: João Mário Domingos [Nikita: replaced soc:pmu to riscv-pmu/id] Signed-off-by: Nikita Shubin Tested-by: Nikita Shubin --- v2->v3: - Change 'soc/soc:pmu/id' to 'riscv-pmu/id' --- drivers/perf/riscv_pmu.c | 18 ++++++++ tools/perf/arch/riscv/util/Build | 1 + tools/perf/arch/riscv/util/header.c | 66 +++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 tools/perf/arch/riscv/util/header.c diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index b2b8d2074ed0..d1aa4e0e527f 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -17,6 +17,23 @@ #include +PMU_FORMAT_ATTR(event, "config:0-63"); + +static struct attribute *riscv_arch_formats_attr[] = { + &format_attr_event.attr, + NULL, +}; + +static struct attribute_group riscv_pmu_format_group = { + .name = "format", + .attrs = riscv_arch_formats_attr, +}; + +static const struct attribute_group *riscv_pmu_attr_groups[] = { + &riscv_pmu_format_group, + NULL, +}; + static unsigned long csr_read_num(int csr_num) { #define switchcase_csr_read(__csr_num, __val) {\ @@ -307,6 +324,7 @@ struct riscv_pmu *riscv_pmu_alloc(void) cpuc->events[i] = NULL; } pmu->pmu = (struct pmu) { + .attr_groups = riscv_pmu_attr_groups, .event_init = riscv_pmu_event_init, .add = riscv_pmu_add, .del = riscv_pmu_del, diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build index 7d3050134ae0..603dbb5ae4dc 100644 --- a/tools/perf/arch/riscv/util/Build +++ b/tools/perf/arch/riscv/util/Build @@ -1,4 +1,5 @@ perf-y += perf_regs.o +perf-y += header.o perf-$(CONFIG_DWARF) += dwarf-regs.o perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c new file mode 100644 index 000000000000..98d40b87c9f3 --- /dev/null +++ b/tools/perf/arch/riscv/util/header.c @@ -0,0 +1,66 @@ +#include +#include +#include +#include +#include "../../util/debug.h" +#include "../../util/header.h" + +#define STR_LEN 1024 +#define ID_SIZE 64 + +static int _get_cpuid(char *buf, size_t sz) +{ + const char *sysfs = sysfs__mountpoint(); + u64 id = 0; + char path[PATH_MAX]; + FILE *file; + + if (!sysfs || sz < ID_SIZE) + return -EINVAL; + + scnprintf(path, PATH_MAX, "%s/devices/platform/riscv-pmu/id", + sysfs); + + file = fopen(path, "r"); + if (!file) { + pr_debug("fopen failed for file %s\n", path); + return -EINVAL; + } + if (!fgets(buf, ID_SIZE, file)) { + fclose(file); + return -EINVAL; + } + + fclose(file); + + /*Check if value is numeric and remove special characters*/ + id = strtoul(buf, NULL, 16); + if (!id) + return -EINVAL; + scnprintf(buf, ID_SIZE, "0x%lx", id); + + return 0; +} + +char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused) +{ + char *buf = NULL; + int res; + + if (!pmu) + return NULL; + + buf = malloc(ID_SIZE); + if (!buf) + return NULL; + + /* read id */ + res = _get_cpuid(buf, ID_SIZE); + if (res) { + pr_err("failed to get cpuid string for PMU %s\n", pmu->name); + free(buf); + buf = NULL; + } + + return buf; +}