From patchwork Tue Jun 7 14:47:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12872034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73D5DC43334 for ; Tue, 7 Jun 2022 14:49:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=96/9tZF5uiQ3fobBPjGx5diQ7uV0xgG3RFf9dpIn2SY=; b=25pkLn+wWKSifl hmzwDCCI68sahgfkYnWR7i7PQTVpSdGWBNdOzU3CoCZEsqdg3LZayKsCR5lcP6wFPYDpIxVCidyXO LxCqaGCRddMdCcpDzAOpUrNMwMtXZAP72LmLBa1NWGDITNnk8O8y7tZZzRPe7smbu8xtz7zd+Gpij Mr+aiZb/G3RuZ99ZDUIjjZ5y6YBerdimywZV+j3g5kxGOsHp8g1tU+0Y5VQLKx4VEkmRQSsiVV+nW BvqyLfUrpP+uQ+p3KIVgIE/gn6ttA93kD4n2FGXOaeZqWtqlFWpVGEbFVaiotSjm2L5UDjVpyLY0J vI7nUkDfh3BsuWbMKg6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyaVO-0089po-OV; Tue, 07 Jun 2022 14:48:26 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyaV5-0089gy-7a for linux-arm-kernel@lists.infradead.org; Tue, 07 Jun 2022 14:48:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1654613286; x=1686149286; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=CZJWqgxwvCwWXufhzXjvG8+KNQ3coiyjK70Ldxx9G9E=; b=vov7HgwG+QIaxgHZfyna4HEBRXlycIBR9wxFJ/5166BiX4GxuTtQ4jwG s4fyWgRDZEDbLH+26aN8ZkofRyUqPsSQVgyDzdmhVxlG9timWGMILysia 1yA9/0FJWpKJZ3dnOWA+3tUQDrkASINm1MCK0wqD7+ZYbk/tWLQMICI7N 0A8REdbTqo23i2+Uc3mxakIW3WP5gih6Bm4IA6SX3fvmpyFPopJjRniZ8 vHnUESFhKPRaZpalEsbMv5E31NwjEQhpyjIME51L3U22bd/tMjQjxfGGn nrAgNNkD3Y6TpsE7MW0rmwV4tKAMnVFvANMr3xDFIRYlBeZzLECQAkkcH Q==; X-IronPort-AV: E=Sophos;i="5.91,284,1647327600"; d="scan'208";a="162250883" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Jun 2022 07:48:06 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 7 Jun 2022 07:48:04 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 7 Jun 2022 07:48:01 -0700 From: Kavyasree Kotagiri To: , , , CC: , , , , Subject: [PATCH v2 3/3] mfd: atmel-flexcom: Add support for lan966x flexcom chip-select configuration Date: Tue, 7 Jun 2022 20:17:40 +0530 Message-ID: <20220607144740.14937-4-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220607144740.14937-1-kavyasree.kotagiri@microchip.com> References: <20220607144740.14937-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_074807_395585_5623C5DA X-CRM114-Status: GOOD ( 20.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org LAN966x SoC have 5 flexcoms. Each flexcom has 2 chip-selects. For each chip select of each flexcom there is a configuration register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration register is 21 because there are 21 shared pins on each of which the chip select can be mapped. Each bit of the register represents a different FLEXCOM_SHARED pin. Signed-off-by: Kavyasree Kotagiri --- v1 -> v2: - use GENMASK for mask, macros for maximum allowed values. - use u32 values for flexcom chipselects instead of strings. - disable clock in case of errors. drivers/mfd/atmel-flexcom.c | 93 ++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 33caa4fba6af..ac700a85b46f 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -28,15 +28,68 @@ #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ FLEX_MR_OPMODE_MASK) +/* LAN966x flexcom shared register offsets */ +#define FLEX_SHRD_SS_MASK_0 0x0 +#define FLEX_SHRD_SS_MASK_1 0x4 +#define FLEX_SHRD_PIN_MAX 20 +#define FLEX_CS_MAX 1 +#define FLEX_SHRD_MASK GENMASK(20, 0) + +struct atmel_flex_caps { + bool has_flx_cs; +}; + struct atmel_flexcom { void __iomem *base; + void __iomem *flexcom_shared_base; u32 opmode; struct clk *clk; }; +static int atmel_flexcom_lan966x_cs_config(struct platform_device *pdev) +{ + struct atmel_flexcom *ddata = dev_get_drvdata(&pdev->dev); + struct device_node *np = pdev->dev.of_node; + u32 flx_shrd_pins[2], flx_cs[2], val; + int err, i, count; + + count = of_property_count_u32_elems(np, "microchip,flx-shrd-pins"); + if (count <= 0 || count > 2) { + dev_err(&pdev->dev, "Invalid %s property (%d)\n", "flx-shrd-pins", + count); + return -EINVAL; + } + + err = of_property_read_u32_array(np, "microchip,flx-shrd-pins", flx_shrd_pins, count); + if (err) + return err; + + err = of_property_read_u32_array(np, "microchip,flx-cs", flx_cs, count); + if (err) + return err; + + for (i = 0; i < count; i++) { + if (flx_shrd_pins[i] > FLEX_SHRD_PIN_MAX) + return -EINVAL; + + if (flx_cs[i] > FLEX_CS_MAX) + return -EINVAL; + + val = ~(1 << flx_shrd_pins[i]) & FLEX_SHRD_MASK; + + if (flx_cs[i] == 0) + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_0); + else + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_1); + } + + return 0; +} + static int atmel_flexcom_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + const struct atmel_flex_caps *caps; struct resource *res; struct atmel_flexcom *ddata; int err; @@ -76,13 +129,51 @@ static int atmel_flexcom_probe(struct platform_device *pdev) */ writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); + caps = of_device_get_match_data(&pdev->dev); + if (!caps) { + dev_err(&pdev->dev, "Could not retrieve flexcom caps\n"); + clk_disable_unprepare(ddata->clk); + return -EINVAL; + } + + if (caps->has_flx_cs) { + ddata->flexcom_shared_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + if (IS_ERR(ddata->flexcom_shared_base)) { + clk_disable_unprepare(ddata->clk); + return dev_err_probe(&pdev->dev, + PTR_ERR(ddata->flexcom_shared_base), + "failed to get flexcom shared base address\n"); + } + + err = atmel_flexcom_lan966x_cs_config(pdev); + if (err) { + clk_disable_unprepare(ddata->clk); + return err; + } + } + clk_disable_unprepare(ddata->clk); return devm_of_platform_populate(&pdev->dev); } +static const struct atmel_flex_caps atmel_flexcom_caps = {}; + +static const struct atmel_flex_caps lan966x_flexcom_caps = { + .has_flx_cs = true, +}; + static const struct of_device_id atmel_flexcom_of_match[] = { - { .compatible = "atmel,sama5d2-flexcom" }, + { + .compatible = "atmel,sama5d2-flexcom", + .data = &atmel_flexcom_caps, + }, + + { + .compatible = "microchip,lan966x-flexcom", + .data = &lan966x_flexcom_caps, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match);