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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 63s5qDr64uwB4Y5GFws0GM6SOV5rLb4ZRsKkWZdkmJQzDFWi5ce8ooO7IDTP5znIAf4Garguae30vzOhcdchZAqHvRlbP3Hh9FNGffyYaxttgTxlX7p6Tj4U5wcxN8e0VR4o521LFs8pLYYv5IOQWsJd1JjAGNteP8jq7ALSqbf7xUkQgPqCfSuiFjK0RklGlDhMvnrgEHx2gAyL0z/kCy/BOGYroukDJXOjy5xdl5rlsDEmXc/tSrITnrnPqfh2x8hNwvtukm5QbckhFbtYQ3jSQham0XgfbM9Z+PO07nC2jw90NS76cFjFSW6C3r/K/wcQp5GUwCWamg8JUAoK///QEhGTtApVzf1315as04T8n49VO1xwdf8rqE1QuTcgL3JpKXdL578iXXBhCRvxxl/9wlADQUlcjqAHwLTJ2WNSe8zkuf75Hr4E8AVlpZQVS6l5td39FDiF5YcbOUW54+dorQ5eAWz4ClVhiHYJI/Y07SNcFf68GIuN8HeADNEZtkKuGWnrrz3BSgUnYZMoNR9NeipN1sFvbC4on3rbztkog8tRT0qkMD8zfMXzniO6+SyvrRo4guKAOyFjglBFXGBB6L134HikrSXKaBdL6+0REUMLATF3RvV9yj4CmzOxFB+2UkRFOZE+1+qLxx+3PSEsscvkkg7VSmwF5TZTmmv5TSMG39oRL1I3/bEQhBLV3fRm7le+2o5xDH4Dm8zLiXMwpVrfAA/XAwHAVQrzjqyZ/ZZWMCR67rfACwnJ6TAW13fDnvAIB+7uX0hB4IBsBQeCZerZtvFtsncS2jvc8ul4cuhhY0JYliO/bSipqJJmzbMoKQKLPh9TkPkhV4n4jxJNSsPvcTkUU4+c63r8WGhJ5/HvA+XU4OZGZeOHsdHMLqOhmAJAviSpYGAR8YHabNW84JmCtEy++48DDmnbT+OhTj9JqPqRQ+Km0AfcryOKa+gLO4ftQBF0Q65Nz3j8COqDAv/9qal+rpPbrsxhKSB+fhPrrWbsv54C3Mu1fhJLHt/jKXLDn9v262FF8JSPA6J4YqzXwEcqj258dXAATXTWLNdK7+rrAqviKD11wRal2cp+SDYCnchCEhyr5hTLMRix1MomuErsN40Q+g7o/PVtSSZ95MZmlAZ2NZ2rMaxC6XC+b2wHhfDLTIkLYHFqLSR427/23ySu104gWDp4Uk56pstzslf8jii3oV5/tsZPZSU/IGBhy+wAc++Gcn5kgs9Z4I96Kt8k4lTxpNFPvDs5nZGnbVMLvvkvyhT/PC5RWY+KgyeGs8XN7ROiOeQj9vCZFVJ+IXcHHuOABSc17m12WihnY+0oh4pflmAgndaxvUj45uKvAentRp/FHd3MlReoEnbednLiFB9ju2701XZy98IW/1zPaQcJ+voL5FMXaDo0zMwQJK71rT/+QRe+NQUQtDndwbSKJRKeh7WV4YX46O89QaFj2WgYjF/pHBeLq607PaUTn3Gx0+aQ4jW7DYC39YdaR6nUAEcI4gTaOo+Au+GGXZeMWZYCb+/KKY1yxp4xKcSSUjelwTuUOzk7sFiXCdtLCEfb7QyGSMXGoSvIR5ivYylakXj2zDCdtUncSuBqta16CboAe6biLyX2y58Ai+4FGEoWQW8Ru4nvkL4KS8VkaSoTmUsoOSZTN7oBg/NRpKxcmp4OG3G90JkxhbvHrRjb75t9q7HyU6XPp3K911RpRlE/mgz0q+axv3Vn5YUPP2mZE8zm7qJ/ABlgPA== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 720db5c4-f102-47da-6d68-08da493c8890 X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2022 10:49:16.7033 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WbIIKyGVf+Mtx8pxVH7anO2ELFlGVRaw2QrKQLoIckp6f8PSIDZ3qIu7+eTfhAxzWkTAsl5NJ/T+ofwGq13hOQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8977 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220608_034923_360185_C7F42618 X-CRM114-Status: GOOD ( 11.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that runtime PM support was added in this driver, we have to enable power before accessing irqchip registers. And, after the access is done, we should disable power. This patch calls pm_runtime_get_sync() in ->irq_unmask() and pm_runtime_put() in ->irq_mask() to make sure power is managed for the register access. Fixes: 4730d2233311 ("irqchip/imx-irqsteer: Add runtime PM support") Cc: Thomas Gleixner Cc: Marc Zyngier Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Lucas Stach Signed-off-by: Liu Ying Reported-by: Lucas Stach Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-imx-irqsteer.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-imx-irqsteer.c b/drivers/irqchip/irq-imx-irqsteer.c index 96230a04ec23..a5eabe71e8ab 100644 --- a/drivers/irqchip/irq-imx-irqsteer.c +++ b/drivers/irqchip/irq-imx-irqsteer.c @@ -45,11 +45,14 @@ static int imx_irqsteer_get_reg_index(struct irqsteer_data *data, static void imx_irqsteer_irq_unmask(struct irq_data *d) { + struct device *dev = d->domain->dev; struct irqsteer_data *data = d->chip_data; int idx = imx_irqsteer_get_reg_index(data, d->hwirq); unsigned long flags; u32 val; + pm_runtime_get_sync(dev); + raw_spin_lock_irqsave(&data->lock, flags); val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); val |= BIT(d->hwirq % 32); @@ -59,6 +62,7 @@ static void imx_irqsteer_irq_unmask(struct irq_data *d) static void imx_irqsteer_irq_mask(struct irq_data *d) { + struct device *dev = d->domain->dev; struct irqsteer_data *data = d->chip_data; int idx = imx_irqsteer_get_reg_index(data, d->hwirq); unsigned long flags; @@ -69,6 +73,8 @@ static void imx_irqsteer_irq_mask(struct irq_data *d) val &= ~BIT(d->hwirq % 32); writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); raw_spin_unlock_irqrestore(&data->lock, flags); + + pm_runtime_put(dev); } static const struct irq_chip imx_irqsteer_irq_chip = {