From patchwork Thu Jun 9 08:32:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12875005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9ACAC43334 for ; Thu, 9 Jun 2022 08:33:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=X7OaPnnvuHzqT6qlNyN6HHdK5Bvg1Z3o0+SJLRtl7pE=; b=rHKDnWdx/wySm0 S4FefyAR3hr4atJu5rzTYPEMAKx6BaLmL0mhkD8hnQl4EU3uxqbjPhKbb420B2u+AZPvN955Y0xWh gxMV+kW6VxOOhioHIfXke21VCxZU+RSyVCC6I418v5Wh4Z9kkA51j3lp6tIk73FwnG0++RVufNHjP RjiU6pTZ8QfqLU/xfSpAHnnZFG+TXV7DBXhwcpyGvPrTZUl8Px8oD5t2kr/IkUALH+ZJs+mfMu189 DHNGiM9LhrXIQsyo1BJfywQEpiQvoMZCY+e1ZsDu29P4ngsJ2k+jg/7uCmb3swl8oTOeSqBNdwd0J LPndKoZuXHcu5p9ghgUA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzDat-000GVa-U3; Thu, 09 Jun 2022 08:32:44 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzDYT-000FMU-Uo for linux-arm-kernel@lists.infradead.org; Thu, 09 Jun 2022 08:30:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1654763413; x=1686299413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qXDN4Bm9sZWZMrQi68BjPeTX8YAr3ZcCdZ3+izwSkus=; b=XbiQ5qtkEPrAkdIOmkExC2XmsCMAE/GcUP8CV3kKUySZ63IP8igG0PT0 7Ai9i51XvPvFc47d0trwVsKLHVSWiB5x3v4fIKEB3ryXGe1N11iwhcBSY F37Kbt+muqB8t0m0/hhPH/M8f8wSQ2CHBACPfIXQ/3W8VscaVSaqCi3mf r1wf0cW0vM6G6u9tAWWLfLDe1XNfrnWdD4P9GmVi94Qf491GqnumMR1jR KJU1vdZZrxDVcC0D1w/H2pD1UIKJFYBpzXnnYtDjTOH5hmskTNTpaD1mf tGVyvYoKT3Xl5R8SK/qzffVYVCmZk8xpQM7t6z9ZLzus/xsO9KTMaTOSN w==; X-IronPort-AV: E=Sophos;i="5.91,287,1647327600"; d="scan'208";a="99259910" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jun 2022 01:30:13 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 9 Jun 2022 01:30:06 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Jun 2022 01:30:03 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 04/16] iio: adc: at91-sama5d2_adc: handle different EMR.OSR for different hw versions Date: Thu, 9 Jun 2022 11:32:01 +0300 Message-ID: <20220609083213.1795019-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220609083213.1795019-1-claudiu.beznea@microchip.com> References: <20220609083213.1795019-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220609_013014_122012_CE55856E X-CRM114-Status: GOOD ( 16.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SAMA7G5 introduces 64 and 256 oversampling rates. Due to this EMR.OSR is 3 bits long. Change the code to reflect this. Commit prepares the code for the addition of 64 and 256 oversampling rates. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 55 ++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index b76328da0cb2..1ceab097335c 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -138,8 +138,7 @@ struct at91_adc_reg_layout { /* Extended Mode Register */ u16 EMR; /* Extended Mode Register - Oversampling rate */ -#define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) -#define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) +#define AT91_SAMA5D2_EMR_OSR(V, M) (((V) << 16) & (M)) #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 @@ -403,6 +402,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = { * @max_index: highest channel index (highest index may be higher * than the total channel number) * @hw_trig_cnt: number of possible hardware triggers + * @osr_mask: oversampling ratio bitmask on EMR register + * @osr_vals: available oversampling rates */ struct at91_adc_platform { const struct at91_adc_reg_layout *layout; @@ -414,6 +415,8 @@ struct at91_adc_platform { unsigned int max_channels; unsigned int max_index; unsigned int hw_trig_cnt; + unsigned int osr_mask; + unsigned int osr_vals; }; /** @@ -612,6 +615,10 @@ static const struct at91_adc_platform sama5d2_platform = { .max_index = AT91_SAMA5D2_MAX_CHAN_IDX, #define AT91_SAMA5D2_HW_TRIG_CNT 3 .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT, + .osr_mask = GENMASK(17, 16), + .osr_vals = BIT(AT91_SAMA5D2_EMR_OSR_1SAMPLES) | + BIT(AT91_SAMA5D2_EMR_OSR_4SAMPLES) | + BIT(AT91_SAMA5D2_EMR_OSR_16SAMPLES), }; static const struct at91_adc_platform sama7g5_platform = { @@ -627,6 +634,10 @@ static const struct at91_adc_platform sama7g5_platform = { .max_index = AT91_SAMA7G5_MAX_CHAN_IDX, #define AT91_SAMA7G5_HW_TRIG_CNT 3 .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, + .osr_mask = GENMASK(18, 16), + .osr_vals = BIT(AT91_SAMA5D2_EMR_OSR_1SAMPLES) | + BIT(AT91_SAMA5D2_EMR_OSR_4SAMPLES) | + BIT(AT91_SAMA5D2_EMR_OSR_16SAMPLES), }; static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -725,34 +736,45 @@ static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) at91_adc_writel(st, EOC_IER, BIT(channel)); } -static void at91_adc_config_emr(struct at91_adc_state *st) +static int at91_adc_config_emr(struct at91_adc_state *st, + u32 oversampling_ratio) { /* configure the extended mode register */ unsigned int emr = at91_adc_readl(st, EMR); + unsigned int osr_mask = st->soc_info.platform->osr_mask; + unsigned int osr_vals = st->soc_info.platform->osr_vals; /* select oversampling per single trigger event */ emr |= AT91_SAMA5D2_EMR_ASTE(1); /* delete leftover content if it's the case */ - emr &= ~AT91_SAMA5D2_EMR_OSR_MASK; + emr &= ~osr_mask; /* select oversampling ratio from configuration */ - switch (st->oversampling_ratio) { + switch (oversampling_ratio) { case AT91_OSR_1SAMPLES: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) & - AT91_SAMA5D2_EMR_OSR_MASK; + if (!(osr_vals & BIT(AT91_SAMA5D2_EMR_OSR_1SAMPLES))) + return -EINVAL; + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES, + osr_mask); break; case AT91_OSR_4SAMPLES: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) & - AT91_SAMA5D2_EMR_OSR_MASK; + if (!(osr_vals & BIT(AT91_SAMA5D2_EMR_OSR_4SAMPLES))) + return -EINVAL; + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES, + osr_mask); break; case AT91_OSR_16SAMPLES: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) & - AT91_SAMA5D2_EMR_OSR_MASK; + if (!(osr_vals & BIT(AT91_SAMA5D2_EMR_OSR_16SAMPLES))) + return -EINVAL; + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, + osr_mask); break; } at91_adc_writel(st, EMR, emr); + + return 0; } static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) @@ -1643,6 +1665,7 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, int val, int val2, long mask) { struct at91_adc_state *st = iio_priv(indio_dev); + int ret = 0; if (iio_buffer_enabled(indio_dev)) return -EBUSY; @@ -1656,12 +1679,14 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, mutex_lock(&st->lock); if (val == st->oversampling_ratio) goto unlock; - st->oversampling_ratio = val; /* update ratio */ - at91_adc_config_emr(st); + ret = at91_adc_config_emr(st, val); + if (ret) + goto unlock; + st->oversampling_ratio = val; unlock: mutex_unlock(&st->lock); - return 0; + return ret; case IIO_CHAN_INFO_SAMP_FREQ: if (val < st->soc_info.min_sample_rate || val > st->soc_info.max_sample_rate) @@ -1834,7 +1859,7 @@ static void at91_adc_hw_init(struct iio_dev *indio_dev) at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); /* configure extended mode register */ - at91_adc_config_emr(st); + at91_adc_config_emr(st, st->oversampling_ratio); } static ssize_t at91_adc_get_fifo_state(struct device *dev,