From patchwork Thu Jun 9 08:42:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12875058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D9FAC433EF for ; Thu, 9 Jun 2022 08:55:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CeM34GEvETzjbx5dfBMf3s0I/Ab/oRA0bz0tBXqqUoM=; b=w+/NAOomTXk2LW xoMqgakbx15V4pExyUAB0wFejjovO68pZTE11jX5xbSt3540FsKBbNBmyPU4fWS12ELIAQ9atS6sw bMtfAHiMH0tOvV1Vc0Q+fKclf1PEh44D5M3i7w2ZqWXW0TAj7XHiMYEP32vRnAicMJR+sYKB9aS3L bB3EMj1I43bBA+4lRyDfDLJQB3GC7NtpmZzrgTtofXorwq1T6DOuc70zSJExwg4flA0E0gXbfuId1 o8GqxPY/icR55cN4msLeeQ2mxFpCWOMgGoo5+AjbJzrZP4TcwTX7gpOcJPvsks36bC2OBM79azTz8 wy4fYe0/hbf0Qnvt86PA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzDvt-000QvD-Ck; Thu, 09 Jun 2022 08:54:26 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzDiI-000Jn1-HM for linux-arm-kernel@lists.infradead.org; Thu, 09 Jun 2022 08:40:24 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1654764022; x=1686300022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jg1QYiymxreKsxc+YO5AbvU8CTlNLdTtmlxGp6mj7yU=; b=lFsZ6AwzdsFoauOmhFt9BswmWgvJ6TEHuBmZ329ihCBgj5AhZcsJhCrW Mh82hZWYGfRuWvDd72IM0DZwwrm29gZtRhCoar8ILgfNeE2zWdCX7ElHk C3zX3dUm8rrgNq9yoqyFfxQ4+/BTJOIu/sUnopsBkCkmTLS970LwvBBQz 0kQX/jLHi/jzUVWXuNxzrBhMVWUsJm3X38N4oRe53rvrqiA03Cp840nRP KJdEm8Q81kYGED8yqM2WosLLcgAgOgfXBlwbvhPVvK8c4ZUMA+SEMuzBV ER4c5xnDrBfUpZLddy88m7nwCOTYFybJtmSBDGT+Fr9CnqhAVGjH2gU6w g==; X-IronPort-AV: E=Sophos;i="5.91,287,1647327600"; d="scan'208";a="159542994" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jun 2022 01:40:21 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 9 Jun 2022 01:40:21 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Jun 2022 01:40:18 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 1/3] spi: atmel-quadspi: add runtime pm support Date: Thu, 9 Jun 2022 11:42:44 +0300 Message-ID: <20220609084246.1795419-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220609084246.1795419-1-claudiu.beznea@microchip.com> References: <20220609084246.1795419-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220609_014022_671773_6E3BE8E1 X-CRM114-Status: GOOD ( 16.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add runtime PM support for atmel-quadspi which will disable/enable QSPI clocks on proper runtime_suspend/runtime_resume ops. Signed-off-by: Claudiu Beznea --- drivers/spi/atmel-quadspi.c | 100 ++++++++++++++++++++++++++++++++---- 1 file changed, 91 insertions(+), 9 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 480c0c8c18e4..6a9327f3c5b4 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -21,6 +21,7 @@ #include #include #include +#include #include /* QSPI register offsets */ @@ -417,9 +418,13 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) if (op->addr.val + op->data.nbytes > aq->mmap_size) return -ENOTSUPP; + err = pm_runtime_resume_and_get(&aq->pdev->dev); + if (err < 0) + return err; + err = atmel_qspi_set_cfg(aq, op, &offset); if (err) - return err; + goto pm_runtime_put; /* Skip to the final steps if there is no data */ if (op->data.nbytes) { @@ -441,7 +446,7 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) /* Poll INSTRuction End status */ sr = atmel_qspi_read(aq, QSPI_SR); if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) - return err; + goto pm_runtime_put; /* Wait for INSTRuction End interrupt */ reinit_completion(&aq->cmd_completion); @@ -452,6 +457,9 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) err = -ETIMEDOUT; atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR); +pm_runtime_put: + pm_runtime_mark_last_busy(&aq->pdev->dev); + pm_runtime_put_autosuspend(&aq->pdev->dev); return err; } @@ -472,6 +480,7 @@ static int atmel_qspi_setup(struct spi_device *spi) struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); unsigned long src_rate; u32 scbr; + int ret; if (ctrl->busy) return -EBUSY; @@ -488,9 +497,16 @@ static int atmel_qspi_setup(struct spi_device *spi) if (scbr > 0) scbr--; + ret = pm_runtime_resume_and_get(ctrl->dev.parent); + if (ret < 0) + return ret; + aq->scr = QSPI_SCR_SCBR(scbr); atmel_qspi_write(aq->scr, aq, QSPI_SCR); + pm_runtime_mark_last_busy(ctrl->dev.parent); + pm_runtime_put_autosuspend(ctrl->dev.parent); + return 0; } @@ -621,11 +637,24 @@ static int atmel_qspi_probe(struct platform_device *pdev) if (err) goto disable_qspick; + pm_runtime_set_autosuspend_delay(&pdev->dev, 500); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_get_noresume(&pdev->dev); + atmel_qspi_init(aq); err = spi_register_controller(ctrl); - if (err) + if (err) { + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); goto disable_qspick; + } + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); return 0; @@ -641,9 +670,18 @@ static int atmel_qspi_remove(struct platform_device *pdev) { struct spi_controller *ctrl = platform_get_drvdata(pdev); struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); + int ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) + return ret; spi_unregister_controller(ctrl); atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); + + pm_runtime_disable(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + clk_disable_unprepare(aq->qspick); clk_disable_unprepare(aq->pclk); return 0; @@ -653,10 +691,19 @@ static int __maybe_unused atmel_qspi_suspend(struct device *dev) { struct spi_controller *ctrl = dev_get_drvdata(dev); struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); - clk_disable_unprepare(aq->qspick); - clk_disable_unprepare(aq->pclk); + + pm_runtime_mark_last_busy(dev); + pm_runtime_force_suspend(dev); + + clk_unprepare(aq->qspick); + clk_unprepare(aq->pclk); return 0; } @@ -665,19 +712,54 @@ static int __maybe_unused atmel_qspi_resume(struct device *dev) { struct spi_controller *ctrl = dev_get_drvdata(dev); struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); + int ret; - clk_prepare_enable(aq->pclk); - clk_prepare_enable(aq->qspick); + clk_prepare(aq->pclk); + clk_prepare(aq->qspick); + + ret = pm_runtime_force_resume(dev); + if (ret < 0) + return ret; atmel_qspi_init(aq); atmel_qspi_write(aq->scr, aq, QSPI_SCR); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; +} + +static int __maybe_unused atmel_qspi_runtime_suspend(struct device *dev) +{ + struct spi_controller *ctrl = dev_get_drvdata(dev); + struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); + + clk_disable(aq->qspick); + clk_disable(aq->pclk); + return 0; } -static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend, - atmel_qspi_resume); +static int __maybe_unused atmel_qspi_runtime_resume(struct device *dev) +{ + struct spi_controller *ctrl = dev_get_drvdata(dev); + struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); + int ret; + + ret = clk_enable(aq->pclk); + if (ret) + return ret; + + return clk_enable(aq->qspick); +} + +static const struct dev_pm_ops __maybe_unused atmel_qspi_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(atmel_qspi_suspend, atmel_qspi_resume) + SET_RUNTIME_PM_OPS(atmel_qspi_runtime_suspend, + atmel_qspi_runtime_resume, NULL) +}; static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};