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Thu, 09 Jun 2022 17:16:03 -0700 (PDT) Received: from T3500-3.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id gw24-20020a17090b0a5800b001e0d197898dsm3702073pjb.3.2022.06.09.17.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 17:16:01 -0700 (PDT) From: William Zhang To: Linux ARM List Cc: anand.gore@broadcom.com, f.fainelli@gmail.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, samyon.furman@broadcom.com, Broadcom Kernel List , kursad.oney@broadcom.com, philippe.reynes@softathome.com, tomer.yacoby@broadcom.com, William Zhang , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: dts: Add DTS files for bcmbca SoC BCM6813 Date: Thu, 9 Jun 2022 17:15:33 -0700 Message-Id: <20220610001534.14275-3-william.zhang@broadcom.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220610001534.14275-1-william.zhang@broadcom.com> References: <20220610001534.14275-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220609_171604_993533_8B875926 X-CRM114-Status: GOOD ( 18.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the SoC description DTS header and bcm96813.dts is a simple DTS file for Broadcom BCM96813 Reference board that only enable the UART port. Signed-off-by: William Zhang --- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 128 ++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm96813.dts | 30 ++++ 3 files changed, 160 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile index cee920bea124..8c6676a69fcb 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb \ bcm96858.dtb \ bcm94912.dtb \ bcm963146.dtb \ - bcm96856.dtb + bcm96856.dtb \ + bcm96813.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi new file mode 100644 index 000000000000..c3e6197be808 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6813", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts new file mode 100644 index 000000000000..af17091ae764 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6813.dtsi" + +/ { + model = "Broadcom BCM96813 Reference Board"; + compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};