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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lars Povlsen , Steen Hegelund , UNGLinuxDriver@microchip.com, Linus Walleij , Wolfram Sang , Terry Bowman , Andy Shevchenko Subject: [PATCH v9 net-next 6/7] dt-bindings: mfd: ocelot: add bindings for VSC7512 Date: Fri, 10 Jun 2022 10:56:54 -0700 Message-Id: <20220610175655.776153-7-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220610175655.776153-1-colin.foster@in-advantage.com> References: <20220610175655.776153-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR19CA0070.namprd19.prod.outlook.com (2603:10b6:300:94::32) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c15ccba7-07ad-45e8-07ef-08da4b0aa3f3 X-MS-TrafficTypeDiagnostic: DM6PR10MB3356:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cZkGWSdrytd0WUDHZDgtaVsZ8DXRlXQ4eBE+OZTNG1Vg7cxMB+jeaUV2hN4mZiQQUk/qd0GbHSn5JICm9McRAcs/o0Ct1Uzu4v0AyUbkY6hRbOwKJeP9JzPNHKB+JpBK1AG/ItVyN1WUo7E6Mb3wZZM0uyrWgZAbCbIHn/OVxFRCV1VXQTg65TOHFTuXcfb26gjuC3NLE1TK2W7eivr6c1Dc1vrQgOKhwWWd5blicbAxGdlSPloXd9AANa9La7cgUtnN8OlXcvVmb2aUIJhcxkzAC5sP8uhoemBtXNHPtCEAYbgtVGtH9HC03SO4vChrQHfJe59g1ZNaILRAjwXu3eMvedI0u7Uti3zp2b4CTsD4CK5GVZAykJhBpeg7QtRO0o8y/8epsiW0SssvbW7abdsjGml2+rsfOhAi5jzEH5q75vs0ho1lRIu1mWMCidxwtVUoDAJWHejtsIC9+h2JSdSVqcM4JsfuCQLM0+VPS81lfgY33WwnOzxCtjarjP5PGSDj+bmGjWsOy5TXQGe6cjf/mLUsCqWhWN2qKieuxjj76iXtJWyjO0vkT45va65LdMW/pNgy2An7/FK0AOJZ0ZVdf53chu4ITUqeIAWgHppvS2VJZnPnlTcTcNIcmJsCXPBgiTFbPOz7Gb4JCFGxdKAu7Rvx8HjIJE7gbZS0F6+gStIVdeldum3pyL10BiQKKtn1BlnG+ESW6Z5xp5TSXU2bCWgj+c6IV/oKeLGTuV3OXIzdOuYMDlVDhgrh0dS97EsVTTlY6HtYdqTFheYIB/NqO6hELezwwSJ4qTx1Juo= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(346002)(366004)(396003)(136003)(39830400003)(1076003)(54906003)(316002)(4326008)(52116002)(8676002)(2616005)(86362001)(508600001)(966005)(6512007)(26005)(6506007)(6666004)(41300700001)(6486002)(186003)(83380400001)(2906002)(38350700002)(44832011)(8936002)(36756003)(38100700002)(66556008)(66946007)(66476007)(7416002)(5660300002);DIR:OUT;SFP:1102; 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Signed-off-by: Colin Foster --- .../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml new file mode 100644 index 000000000000..e298ca8d616d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ocelot Externally-Controlled Ethernet Switch + +maintainers: + - Colin Foster + +description: | + The Ocelot ethernet switch family contains chips that have an internal CPU + (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have + the option to be controlled externally, which is the purpose of this driver. + + The switch family is a multi-port networking switch that supports many + interfaces. Additionally, the device can perform pin control, MDIO buses, and + external GPIO expanders. + +properties: + compatible: + enum: + - mscc,vsc7512-spi + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + spi-max-frequency: + maxItems: 1 + +patternProperties: + "^pinctrl@[0-9a-f]+$": + type: object + $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml + + "^gpio@[0-9a-f]+$": + type: object + $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml + properties: + compatible: + enum: + - mscc,ocelot-sgpio + + "^mdio@[0-9a-f]+$": + type: object + $ref: /schemas/net/mscc,miim.yaml + properties: + compatible: + enum: + - mscc,ocelot-miim + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - spi-max-frequency + +additionalProperties: false + +examples: + - | + ocelot_clock: ocelot-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + ocelot-chip@0 { + compatible = "mscc,vsc7512-spi"; + spi-max-frequency = <2500000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0: mdio@7107009c { + compatible = "mscc,ocelot-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7107009c>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + }; + + mdio1: mdio@710700c0 { + compatible = "mscc,ocelot-miim"; + pinctrl-names = "default"; + pinctrl-0 = <&miim1_pins>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x710700c0>; + + sw_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + }; + + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + reg = <0x71070034>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + miim1_pins: miim1-pins { + pins = "GPIO_14", "GPIO_15"; + function = "miim"; + }; + }; + + sgpio: gpio@710700f8 { + compatible = "mscc,ocelot-sgpio"; + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <12500000>; + clocks = <&ocelot_clock>; + microchip,sgpio-port-ranges = <0 15>; + pinctrl-names = "default"; + pinctrl-0 = <&sgpio_pins>; + reg = <0x710700f8>; + + sgpio_in0: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <64>; + }; + + sgpio_out1: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <64>; + }; + }; + }; + }; + +... + diff --git a/MAINTAINERS b/MAINTAINERS index 91b4151c5ad1..119fb4207ba3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14355,6 +14355,7 @@ F: tools/testing/selftests/drivers/net/ocelot/* OCELOT EXTERNAL SWITCH CONTROL M: Colin Foster S: Supported +F: Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml F: include/linux/mfd/ocelot.h OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER