| Message ID | 20220616155836.3401420-3-judyhsiao@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ASoC: rockchip: i2s: switch BCLK to GPIO | expand |
Hi, On Thu, Jun 16, 2022 at 03:58:35PM +0000, Judy Hsiao wrote: > We discoverd that the state of BCLK on, LRCLK off and SD_MODE on > may cause the speaker melting issue. Removing LRCLK while BCLK > is present can cause unexpected output behavior including a large > DC output voltage as described in the Max98357a datasheet. > > In order to: > 1. prevent BCLK from turning on by other component. > 2. keep BCLK and LRCLK being present at the same time > > This patch adjusts the device tree to allow BCLK to switch > to GPIO func before LRCLK output, and switch back during > LRCLK is output. > > Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -1662,9 +1662,10 @@ i2s0: i2s@ff880000 { > dma-names = "tx", "rx"; > clock-names = "i2s_clk", "i2s_hclk"; > clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; > - pinctrl-names = "default"; > + pinctrl-names = "bclk_on", "bclk_off"; > pinctrl-0 = <&i2s0_8ch_bus>; > power-domains = <&power RK3399_PD_SDIOAUDIO>; > + pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; It seems like 'pinctrl-1' may make sense after pinctrl-0, not here. Perhaps you're interacting with my RFC PATCH that removes this 'power-domains' property? https://lore.kernel.org/linux-rockchip/20220613183556.RFC.1.I9ca71105e505f024d53b7e0ba4462230813ebb8d@changeid/ But that most likely isn't landing upstream as-is. Otherwise, this patch looks good to me: Reviewed-by: Brian Norris <briannorris@chromium.org> > #sound-dai-cells = <0>; > status = "disabled"; > };
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index 913d845eb51a..df1647e9d487 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -766,6 +766,16 @@ &i2s0_8ch_bus { <4 RK_PA0 1 &pcfg_pull_none_6ma>; }; +&i2s0_8ch_bus_bclk_off { + rockchip,pins = + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_6ma>, + <3 RK_PD1 1 &pcfg_pull_none_6ma>, + <3 RK_PD2 1 &pcfg_pull_none_6ma>, + <3 RK_PD3 1 &pcfg_pull_none_6ma>, + <3 RK_PD7 1 &pcfg_pull_none_6ma>, + <4 RK_PA0 1 &pcfg_pull_none_6ma>; +}; + /* there is no external pull up, so need to set this pin pull up */ &sdmmc_cd_pin { rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index fbd0346624e6..3981dec6a5a5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1662,9 +1662,10 @@ i2s0: i2s@ff880000 { dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; - pinctrl-names = "default"; + pinctrl-names = "bclk_on", "bclk_off"; pinctrl-0 = <&i2s0_8ch_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -2407,6 +2408,19 @@ i2s0_8ch_bus: i2s0-8ch-bus { <3 RK_PD7 1 &pcfg_pull_none>, <4 RK_PA0 1 &pcfg_pull_none>; }; + + i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { + rockchip,pins = + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; + }; }; i2s1 { @@ -2418,6 +2432,15 @@ i2s1_2ch_bus: i2s1-2ch-bus { <4 RK_PA6 1 &pcfg_pull_none>, <4 RK_PA7 1 &pcfg_pull_none>; }; + + i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { + rockchip,pins = + <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA4 1 &pcfg_pull_none>, + <4 RK_PA5 1 &pcfg_pull_none>, + <4 RK_PA6 1 &pcfg_pull_none>, + <4 RK_PA7 1 &pcfg_pull_none>; + }; }; sdio0 {
We discoverd that the state of BCLK on, LRCLK off and SD_MODE on may cause the speaker melting issue. Removing LRCLK while BCLK is present can cause unexpected output behavior including a large DC output voltage as described in the Max98357a datasheet. In order to: 1. prevent BCLK from turning on by other component. 2. keep BCLK and LRCLK being present at the same time This patch adjusts the device tree to allow BCLK to switch to GPIO func before LRCLK output, and switch back during LRCLK is output. Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> --- .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 10 ++++++++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)