From patchwork Fri Jun 17 13:07:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12885701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 401CAC43334 for ; Fri, 17 Jun 2022 13:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Kb5hehpqk3Lki4vJvmqB2RBiaDUW4FrJiRdaOLJIxFM=; b=leT3TkmCcSW59K WzNRx1CAADUno4soiC5oiJ0GvXIyXIYItOn29UoNfPqZMkBSNS1d7g0TD/zel89pK4Bhawg3Wn6j6 58Sk9c4sctcatd/t50Qd7czr55OPHtI1JlxuLfKGAElswWy+PjaVvUCQAmY7OikOeIF4Ov/UP4yWs I4opdI8/vfh6jEO9cjnMuNdGY5kxH9gm/nmX1Uy4WEi8RIyxxKh7kY6K3b5xo0ccfwwZadHsSEtOk lepy2Mca5en62x7hEJ25Qhty9/4Dh0DbRpJXgogIgCOlwCdvSEBHeNSLvye+z7YTmH4rN/eexVCoz Xotc5Ko0lNKZge/gY71w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o2Bi1-007mDx-MZ; Fri, 17 Jun 2022 13:08:22 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o2Bhi-007m5y-GF for linux-arm-kernel@lists.infradead.org; Fri, 17 Jun 2022 13:08:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1655471282; x=1687007282; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=yeaBSgqP4WX2Wonw/3BYqcLV3KY+P6xrfEoUN94P6/o=; b=LUDqjNTq0ZWwTe97hdAzeXGExpdUnfHfey94bilTphb64fokpI7nV0YL MvuGldaeBJTRoG5anldiGXovJeHg+XDHwgji3+OwrMngEo9kip8H7xZgJ Txy2a0V7swMQP5Sh9d//LHmQfE40uUCcb4fOsKMixaMPgvMgyyNNzNs+h 2ZT1TS9458wh3mnqSlL2QgxITDS1UAsOuvZIxY/0/onY9iJD+F2tbyM3y Hm9EhAqDL8E2T+zkKhrhMbC8XtHQdVtNTRgJ1p0nesBivxCmGx2S1nC1O 2fsD1adWhPkIhn+8EM/FDV+RfTJG/y05SuUJ+TLD+prsCDlgoBIZPsGu9 w==; X-IronPort-AV: E=Sophos;i="5.92,306,1650956400"; d="scan'208";a="163864287" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Jun 2022 06:07:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 17 Jun 2022 06:07:57 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 17 Jun 2022 06:07:54 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , Subject: [PATCH v4 2/3] dt-bindings: mfd: atmel,flexcom: Add new compatible string for lan966x Date: Fri, 17 Jun 2022 18:37:28 +0530 Message-ID: <20220617130729.12072-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220617130729.12072-1-kavyasree.kotagiri@microchip.com> References: <20220617130729.12072-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220617_060802_663436_3532892B X-CRM114-Status: UNSURE ( 9.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri --- v3 -> v4: - Added else condition to allOf:if:then. v2 -> v3: - Add reg property of lan966x missed in v2. v1 -> v2: - Use allOf:if:then for lan966x dt properties .../bindings/mfd/atmel,flexcom.yaml | 80 ++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml index fdb1645d123f..7e0e4d6b1b96 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -18,9 +18,11 @@ properties: compatible: enum: - atmel,sama5d2-flexcom + - microchip,lan966x-flexcom reg: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: maxItems: 1 @@ -47,6 +49,27 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3] + microchip,flx-shrd-pins: + description: Specify the Flexcom shared pins to be used for flexcom + chip-selects. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 20 + + microchip,flx-cs: + description: Flexcom chip selects. Here, value of '0' represents "cts" line + of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents + "rts" line of flexcom USART or "cs1" line of flexcom SPI. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + patternProperties: "^serial@[0-9a-f]+$": description: See atmel-usart.txt for details of USART bindings. @@ -73,6 +96,33 @@ required: - ranges - atmel,flexcom-mode +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan966x-flexcom + + then: + properties: + reg: + minItems: 2 + items: + - description: Flexcom base regsiters map + - description: Flexcom shared registers map + required: + - microchip,flx-shrd-pins + - microchip,flx-cs + + else: + properties: + reg: + maxItems: 1 + items: + - description: Flexcom base regsiters map + microchip,flx-shrd-pins: false + microchip,flx-cs: false + additionalProperties: false examples: @@ -101,4 +151,32 @@ examples: atmel,fifo-size = <32>; }; }; + - | + #include + + flx3: flexcom@e0064000 { + compatible = "microchip,lan966x-flexcom"; + reg = <0xe0064000 0x100>, + <0xe2004180 0x8>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + atmel,flexcom-mode = <2>; + microchip,flx-shrd-pins = <9>; + microchip,flx-cs = <0>; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + }; + }; ...