From patchwork Mon Jun 20 12:10:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12887503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CCD1C433EF for ; Mon, 20 Jun 2022 12:23:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LeH7cGlhDZ04CxoIxLj44UcyfDH8uNlgaWdSgePhivg=; b=JuDtwVhdSFwhAL 7hFV/I0RNwMdD0aJ14pcxxB9HGDbCNLzSLcLdqcqtUJGSMy8QmqwnBk+JLOlAHyOYYKNQzP2S3zlv lTrzNKrpVVDEM+qSDOrZtvkCpYJuv45uUBQOi9VkKwJZB47sf3uDIEdQPXuQvh3Ds0JSCg15HYeeu 3SimbS88pHRU71dlfn8MnsphQRxeb6wAX8AIKGN8t5Q1jqW5cHj93e/gE/pHHC9iu0zSBGXGmkLlQ viV1hxcUKNSVAojetfx3dPQExNa5bDooydqEAQTeZ3XKxvI5BDxkrpFEFrk3nyTHBsJmWWl6kYPlk 3aPVR6k9j6M8gZ76Pzxw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3GQI-000Nm7-7C; Mon, 20 Jun 2022 12:22:30 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3GOW-000N9W-Fe; Mon, 20 Jun 2022 12:20:42 +0000 X-UUID: cb8bb16acd9443bb80132769998e0674-20220620 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:41a837a2-268f-4d84-b323-bcb1074824a6,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:b14ad71,CLOUDID:43d18b2d-1756-4fa3-be7f-474a6e4be921,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: cb8bb16acd9443bb80132769998e0674-20220620 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 92664808; Mon, 20 Jun 2022 05:20:36 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 20 Jun 2022 05:10:40 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 20 Jun 2022 20:10:31 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 20 Jun 2022 20:10:31 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v12 14/14] drm/mediatek: dpi: Add matrix_sel helper Date: Mon, 20 Jun 2022 20:10:28 +0800 Message-ID: <20220620121028.29234-15-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220620121028.29234-1-rex-bc.chen@mediatek.com> References: <20220620121028.29234-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220620_052040_564553_72B2E0B8 X-CRM114-Status: GOOD ( 14.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Guillaume Ranquet Matrix selection is a new feature for both dpi and dpintf of MT8195. Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 220e9b18e2cd..8a9151cb1622 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -135,6 +135,7 @@ struct mtk_dpi_conf { u32 channel_swap_shift; u32 yuv422_en_bit; u32 csc_enable_bit; + bool matrx_sel_support; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -398,6 +399,31 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); } +static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, + enum mtk_dpi_out_color_format format) +{ + u32 matrix_sel = 0; + + if (!dpi->conf->matrx_sel_support) { + dev_info(dpi->dev, "matrix_sel is not supported.\n"); + return; + } + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <= 720) + matrix_sel = 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -405,6 +431,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -412,6 +439,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, true); else @@ -951,6 +979,7 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = { .channel_swap_shift = DPINTF_CH_SWAP, .yuv422_en_bit = DPINTF_YUV422_EN, .csc_enable_bit = DPINTF_CSC_ENABLE, + .matrx_sel_support = true, }; static int mtk_dpi_probe(struct platform_device *pdev) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index f7f0272dbd6a..96c117202d0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -230,4 +230,7 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK (0x1F << 0) + #endif /* __MTK_DPI_REGS_H */