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[92.40.169.63]) by smtp.gmail.com with ESMTPSA id b9-20020adfe309000000b0020d0c9c95d3sm14556677wrj.77.2022.06.20.13.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:20 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, bgoswami@codeaurora.org, gregkh@linuxfoundation.org, rafael@kernel.org, cw00.choi@samsung.com, krzysztof.kozlowski@linaro.org, b.zolnierkie@samsung.com, myungjoo.ham@samsung.com, michael@walle.cc, linus.walleij@linaro.org, brgl@bgdev.pl, tglx@linutronix.de, maz@kernel.org, lee.jones@linaro.org, mani@kernel.org, cristian.ciocaltea@gmail.com, wens@csie.org, tharvey@gateworks.com, rjones@gateworks.com, mazziesaccount@gmail.com, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, jernej.skrabec@gmail.com, samuel@sholland.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-actions@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org Subject: [PATCH 41/49] mfd: stpmic1: Enable mask_writeonly flag for irq chip Date: Mon, 20 Jun 2022 21:06:36 +0100 Message-Id: <20220620200644.1961936-42-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220620_130723_552801_466900B0 X-CRM114-Status: UNSURE ( 9.60 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The STPMIC1 has separate set and clear registers for controlling its interrupt masks. These are volatile registers; writing a '1' will set or clear the corresponding mask bit, and they read as 0. Marking the registers volatile and using the mask_writeonly flag should reduce bus traffic by avoiding a read-modify-write on the mask set/clear registers. Signed-off-by: Aidan MacDonald --- drivers/mfd/stpmic1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c index 11f3d92acbc0..a99f7b45df57 100644 --- a/drivers/mfd/stpmic1.c +++ b/drivers/mfd/stpmic1.c @@ -42,6 +42,8 @@ static const struct regmap_range stpmic1_volatile_ranges[] = { regmap_reg_range(WCHDG_CR, WCHDG_CR), regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4), regmap_reg_range(INT_SRC_R1, INT_SRC_R4), + regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4), + regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4), }; static const struct regmap_access_table stpmic1_readable_table = { @@ -110,6 +112,7 @@ static const struct regmap_irq_chip stpmic1_regmap_irq_chip = { .status_base = INT_PENDING_R1, .mask_base = INT_SET_MASK_R1, .unmask_base = INT_CLEAR_MASK_R1, + .mask_writeonly = true, .ack_base = INT_CLEAR_R1, .num_regs = STPMIC1_PMIC_NUM_IRQ_REGS, .irqs = stpmic1_irqs,