From patchwork Wed Jun 22 17:43:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C612CCA481 for ; Wed, 22 Jun 2022 17:54:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9QujE6miWb9/6lvuP/6+UoGPShAlVd6ByWUBqg7sIqk=; b=o8u4CjYV3unmyj AcDl99B7qjWpNtWZw26oLFvNbuiat/EuVtdffotpiKor26Bs1rIjcrBAu8Kjxjn3YRMyNhJuKKjlg HQo1BSlojusjwzgXurA5u/XUota68iPwmMoPezTWNe4ZdT9w0ct2geWTgoe6d0ERiboc2lRx42URM ANCL4TCMmnQZwbgD1ujfLrp4M/q07ibrV0w3Ytnt1/9iIzFJ2E3Vx9FvDv1B3Ufri8SUC1Vd86R05 qPP+bGahma/8emW5yDwNxMYN6L5t37Yf5QNllwrMwl2YDvq4VriazzPUfjuunl2EdT8ausxtXto3F xtKk9oLw+2Kkck4NG0eQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o44XE-00BlUb-Ao; Wed, 22 Jun 2022 17:53:00 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o44X3-00BlS2-2z for linux-arm-kernel@lists.infradead.org; Wed, 22 Jun 2022 17:52:50 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AEE9761CCC; Wed, 22 Jun 2022 17:52:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19874C341C7; Wed, 22 Jun 2022 17:52:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920368; bh=1iZYkc1hPiqKypGNa6u/smua1y2PeeeLJrraOYdQNQQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SW/lxuVfzJrnygNRxqUc44TTaSGhiNjKqym1g5F/VDZZ7LeFwgL9BDgI+qZIXo4Lq j9a0KRRvNm+cxnsROrEVLoSZZ1Lwnch/GsxGV0vnJjcacyBz4lQJ5vtY/lSsvKrIi+ cBeo9i8pUdQMGl6dDPp7FKjhUQHIsuFreedfp9pfuxItUlj52T0spNHaQcv1uic8vc ovcK9haEtCc267dmGIT9DNqus9dLhjAQIReXpe3T1yGXB3eiNe4hTgegs/iEbfeRES xHFkIZ10RiD2fxfTQzBFxymefJ8EtuPusngZkM5Umbcor5wiCPjIjQmMT0NVl/h+A6 xkFCdT5XtpzFg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Date: Wed, 22 Jun 2022 18:43:50 +0100 Message-Id: <20220622174416.1406282-2-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2928; h=from:subject; bh=1iZYkc1hPiqKypGNa6u/smua1y2PeeeLJrraOYdQNQQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1Ta4JiwcLT2rPnakAPjbPyXMjggczAlvJgtnxoh vqdhCCuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU2gAKCRAk1otyXVSH0PbKB/ wPurrm8Fjvqc+9+m1juFMmt2etCeu1Y8F/0cRf3ddQBpH+5/q7gSy4238zf5iyclb0ln59ffzE/AOu sQzPxiRbTEt6x0PmATOCjSRyBwyxLl6PKObwkZRK/1f/nK22nBROymMVm9+0lGQBswkoErd1pVsNy7 rFM1+KOCaGuxkyeEEAP2qKLMboDrKffGHGrrohrJzMoN7ID2LLD5Dkv7Ni0RZ1xgNS5IbpGIOnOV6v W7iJuvKPwCi6NFIeNsFXljCzeToLwUCNWAgQDVvOF/yXPumrxyCC2lydXgLINGEpQhEKD+Be62BpTB Mg9o5HYiyxNIhp0xD092LxYiAq8wBf X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105249_241335_50EF6C46 X-CRM114-Status: GOOD ( 17.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In 155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT I-caches") we removed all the support fir AIVIVT cache types and renamed all references to the field to say "unknown" since support for AIVIVT caches was removed from the architecture. Some confusion has resulted since the corresponding change to the architecture left the value named as AIVIVT but documented it as reserved in v8, refactor the code so we don't define the constant instead. This will help with automatic generation of this register field since it means we care less about the correspondence with the ARM. No functional change, the value displayed to userspace is unchanged. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cache.h | 1 - arch/arm64/kernel/cpuinfo.c | 27 +++++++++++++++++---------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 7c2181c72116..0cbe75b9e4e5 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -25,7 +25,6 @@ #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) #define ICACHE_POLICY_VPIPT 0 -#define ICACHE_POLICY_RESERVED 1 #define ICACHE_POLICY_VIPT 2 #define ICACHE_POLICY_PIPT 3 diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 8eff0a34ffd4..7ecf9ffb590b 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -33,12 +33,19 @@ DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); static struct cpuinfo_arm64 boot_cpu_data; -static const char *icache_policy_str[] = { - [ICACHE_POLICY_VPIPT] = "VPIPT", - [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", - [ICACHE_POLICY_VIPT] = "VIPT", - [ICACHE_POLICY_PIPT] = "PIPT", -}; +static inline const char *icache_policy_str(int l1ip) +{ + switch (l1ip) { + case ICACHE_POLICY_VPIPT: + return "VPIPT"; + case ICACHE_POLICY_VIPT: + return "VIPT"; + case ICACHE_POLICY_PIPT: + return "PIPT"; + default: + return "RESERVED/UNKNOWN"; + } +} unsigned long __icache_flags; @@ -342,19 +349,19 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) u32 l1ip = CTR_L1IP(info->reg_ctr); switch (l1ip) { - case ICACHE_POLICY_PIPT: - break; case ICACHE_POLICY_VPIPT: set_bit(ICACHEF_VPIPT, &__icache_flags); break; - case ICACHE_POLICY_RESERVED: case ICACHE_POLICY_VIPT: /* Assume aliasing */ set_bit(ICACHEF_ALIASING, &__icache_flags); break; + case ICACHE_POLICY_PIPT: + default: + break; } - pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); + pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); } static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)