From patchwork Thu Jun 23 01:48:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Zhongjin X-Patchwork-Id: 12891638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D02EDC2BBE6 for ; Thu, 23 Jun 2022 01:53:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0kgwHB4pE6uWGdUfW/Fvjmc1peobf/fJuAHGYt2aKTw=; b=LUHyEm3uUft9iP RMniVxm3liDQ4O72Vx3/LWCiFxjK87VsGtacDiooKJb0FqL06OxsXh4sRpXHPVYLpru+x9TFUTsKF 4TP9qBCh5fSrxnSZPOE/pgZlr/oPK0JLYawXvMuhfjOiqiGZ0J3skhErCpcw9RyRlU8R6VWCFu/e6 Css6RE3iUS6UOlzHZi6VWkLxjgGsCcWpjSiZJNWXvGeU7jhoWzjeAZUR1Ucjtt7N0SIfzLa0neRX4 1HIwwBP3DAXf1MGpm3/FMKZWm8yotWkugapuGS036ilfhZy51KTzrPqtS6w9BETP4ZglSiy/QDygI QHQhZqtL9oHBa5HKPFCA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4C1R-00CkOc-PW; Thu, 23 Jun 2022 01:52:41 +0000 Received: from szxga02-in.huawei.com ([45.249.212.188]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4C0e-00Ck1t-Ff for linux-arm-kernel@lists.infradead.org; Thu, 23 Jun 2022 01:51:58 +0000 Received: from dggpemm500021.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4LT3795CDXzShBh; Thu, 23 Jun 2022 09:48:21 +0800 (CST) Received: from dggpemm500013.china.huawei.com (7.185.36.172) by dggpemm500021.china.huawei.com (7.185.36.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 23 Jun 2022 09:51:46 +0800 Received: from ubuntu1804.huawei.com (10.67.175.36) by dggpemm500013.china.huawei.com (7.185.36.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 23 Jun 2022 09:51:46 +0800 From: Chen Zhongjin To: , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v6 03/33] objtool: arm64: Decode add/sub instructions Date: Thu, 23 Jun 2022 09:48:47 +0800 Message-ID: <20220623014917.199563-4-chenzhongjin@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220623014917.199563-1-chenzhongjin@huawei.com> References: <20220623014917.199563-1-chenzhongjin@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.175.36] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpemm500013.china.huawei.com (7.185.36.172) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_185152_909976_160201CB X-CRM114-Status: GOOD ( 12.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Decode aarch64 additions and substractions and create stack_ops for instructions interacting with SP or FP. Signed-off-by: Julien Thierry Signed-off-by: Chen Zhongjin --- tools/objtool/arch/arm64/decode.c | 82 +++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index afe22c4593c8..d8c32703874d 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -15,6 +15,22 @@ #include "../../../arch/arm64/lib/insn.c" +#define is_SP(reg) (reg == AARCH64_INSN_REG_SP) +#define is_FP(reg) (reg == AARCH64_INSN_REG_FP) +#define is_SPFP(reg) (reg == AARCH64_INSN_REG_SP || reg == AARCH64_INSN_REG_FP) + +#define ADD_OP(op) \ + if (!(op = calloc(1, sizeof(*op)))) \ + return -1; \ + else for (list_add_tail(&op->list, ops_list); op; op = NULL) + +static unsigned long sign_extend(unsigned long x, int nbits) +{ + unsigned long sign_bit = (x >> (nbits - 1)) & 1; + + return ((~0UL + (sign_bit ^ 1)) << nbits) | x; +} + bool arch_callee_saved_reg(unsigned char reg) { switch (reg) { @@ -105,6 +121,42 @@ int arch_decode_hint_reg(u8 sp_reg, int *base) return -1; } +static inline void make_add_op(enum aarch64_insn_register dest, + enum aarch64_insn_register src, + int val, struct stack_op *op) +{ + op->dest.type = OP_DEST_REG; + op->dest.reg = dest; + op->src.reg = src; + op->src.type = val != 0 ? OP_SRC_ADD : OP_SRC_REG; + op->src.offset = val; +} + +static void decode_add_sub_imm(u32 instr, bool set_flags, + unsigned long *immediate, + struct stack_op *op) +{ + u32 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, instr); + u32 rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, instr); + + *immediate = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, instr); + + if (instr & AARCH64_INSN_LSL_12) + *immediate <<= 12; + + if ((!set_flags && is_SP(rd)) || is_FP(rd) + || is_SPFP(rn)) { + int value; + + if (aarch64_insn_is_subs_imm(instr) || aarch64_insn_is_sub_imm(instr)) + value = -*immediate; + else + value = *immediate; + + make_add_op(rd, rn, value, op); + } +} + int arch_decode_instruction(struct objtool_file *file, const struct section *sec, unsigned long offset, unsigned int maxlen, unsigned int *len, enum insn_type *type, @@ -112,6 +164,7 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec struct list_head *ops_list) { const struct elf *elf = file->elf; + struct stack_op *op = NULL; u32 insn; if (!is_arm64(elf)) @@ -130,6 +183,35 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec case AARCH64_INSN_CLS_UNKNOWN: WARN("can't decode instruction at %s:0x%lx", sec->name, offset); return -1; + case AARCH64_INSN_CLS_DP_IMM: + /* Mov register to and from SP are aliases of add_imm */ + if (aarch64_insn_is_add_imm(insn) || + aarch64_insn_is_sub_imm(insn)) { + ADD_OP(op) { + decode_add_sub_imm(insn, false, immediate, op); + } + } + else if (aarch64_insn_is_adds_imm(insn) || + aarch64_insn_is_subs_imm(insn)) { + ADD_OP(op) { + decode_add_sub_imm(insn, true, immediate, op); + } + } + break; + case AARCH64_INSN_CLS_DP_REG: + if (aarch64_insn_is_mov_reg(insn)) { + enum aarch64_insn_register rd; + enum aarch64_insn_register rm; + + rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn); + rm = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RM, insn); + if (is_FP(rd) || is_FP(rm)) { + ADD_OP(op) { + make_add_op(rd, rm, 0, op); + } + } + } + break; default: break; }