From patchwork Thu Jun 23 01:48:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Zhongjin X-Patchwork-Id: 12891672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81C5CC43334 for ; Thu, 23 Jun 2022 01:58:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NFIAFhrs3Gr7FI5y6X0TRfpR6WSTjRjGBm56MN64bjw=; b=l0jdz3Gy64VOMV D7wBIMlaxOPrBhyf/g//jctgreNPu2b2UItek4rS7snPrn1Ci8gE3FQYiEePsgSGrIe5xqb+iKOoW 8n1k6t3oeFqUDm5LXZO4htKxn0tUOyuag+dmFgY+XLfiPdmfxwxkUDsQey+7Ma7lW+5rEbqcCrv9i 8Xu2eHPqzrNsIyhq8TtOe+gtdRdWrrt+50SfwcNLBE23DEOsfSUQs16dDRncLBTC6vG+LfG//Q+mx kdEYHEdqFtM1gsF2e+AhOXakB3DVwWTi64j3awocZrfULTqU2yIXoTgvXJgHPkEP3paZqCNFB7yJF ocNbT+84GlMf1pXNyj2Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4C4v-00CmCw-16; Thu, 23 Jun 2022 01:56:18 +0000 Received: from szxga03-in.huawei.com ([45.249.212.189]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4C0i-00Ck1z-La for linux-arm-kernel@lists.infradead.org; Thu, 23 Jun 2022 01:52:02 +0000 Received: from dggpemm500023.china.huawei.com (unknown [172.30.72.57]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4LT3BT12BrzDsK1; Thu, 23 Jun 2022 09:51:13 +0800 (CST) Received: from dggpemm500013.china.huawei.com (7.185.36.172) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 23 Jun 2022 09:51:47 +0800 Received: from ubuntu1804.huawei.com (10.67.175.36) by dggpemm500013.china.huawei.com (7.185.36.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 23 Jun 2022 09:51:46 +0800 From: Chen Zhongjin To: , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v6 06/33] objtool: arm64: Decode load/store instructions Date: Thu, 23 Jun 2022 09:48:50 +0800 Message-ID: <20220623014917.199563-7-chenzhongjin@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220623014917.199563-1-chenzhongjin@huawei.com> References: <20220623014917.199563-1-chenzhongjin@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.175.36] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpemm500013.china.huawei.com (7.185.36.172) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_185157_672525_1F914922 X-CRM114-Status: GOOD ( 11.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Decode load/store operations and create corresponding stack_ops for operations targeting SP or FP. Operations storing/loading multiple registers are split into separate stack_ops storing single registers. Operations modifying the base register get an additional stack_op for the register update. Since the atomic register(s) load/store + base register update gets split into multiple operations, to make sure objtool always sees a valid stack, consider store instruction to perform stack allocations (i.e. modifying the base pointer before the storing) and loads de-allocations (i.e. modifying the base pointer after the load). Signed-off-by: Julien Thierry Signed-off-by: Chen Zhongjin --- tools/objtool/arch/arm64/decode.c | 112 ++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index 19840862f3aa..8ce9d91ff0db 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -132,6 +132,114 @@ static inline void make_add_op(enum aarch64_insn_register dest, op->src.offset = val; } +static inline void make_store_op(enum aarch64_insn_register base, + enum aarch64_insn_register reg, + int offset, struct stack_op *op) +{ + op->dest.type = OP_DEST_REG_INDIRECT; + op->dest.reg = base; + op->dest.offset = offset; + op->src.type = OP_SRC_REG; + op->src.reg = reg; + op->src.offset = 0; +} + +static inline void make_load_op(enum aarch64_insn_register base, + enum aarch64_insn_register reg, + int offset, struct stack_op *op) +{ + op->dest.type = OP_DEST_REG; + op->dest.reg = reg; + op->dest.offset = 0; + op->src.type = OP_SRC_REG_INDIRECT; + op->src.reg = base; + op->src.offset = offset; +} + +static inline bool aarch64_insn_is_ldst_pre(u32 insn) +{ + return aarch64_insn_is_store_pre(insn) || + aarch64_insn_is_load_pre(insn) || + aarch64_insn_is_stp_pre(insn) || + aarch64_insn_is_ldp_pre(insn); +} + +static inline bool aarch64_insn_is_ldst_post(u32 insn) +{ + return aarch64_insn_is_store_post(insn) || + aarch64_insn_is_load_post(insn) || + aarch64_insn_is_stp_post(insn) || + aarch64_insn_is_ldp_post(insn); +} + +static int decode_load_store(u32 insn, unsigned long *immediate, + struct list_head *ops_list) +{ + enum aarch64_insn_register base; + enum aarch64_insn_register rt; + struct stack_op *op; + int size; + int offset; + + if (aarch64_insn_is_store_single(insn) || + aarch64_insn_is_load_single(insn)) + size = 1 << ((insn & GENMASK(31, 30)) >> 30); + else + size = 4 << ((insn >> 31) & 1); + + if (aarch64_insn_is_store_pair(insn) || + aarch64_insn_is_load_pair(insn)) + *immediate = size * sign_extend(aarch64_insn_decode_immediate(AARCH64_INSN_IMM_7, + insn), 7); + else if (aarch64_insn_is_store_imm(insn) || + aarch64_insn_is_load_imm(insn)) + *immediate = size * aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, insn); + else /* load/store_pre/post */ + *immediate = sign_extend(aarch64_insn_decode_immediate(AARCH64_INSN_IMM_9, + insn), 9); + + base = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn); + if (!is_SPFP(base)) + return 0; + + if (aarch64_insn_is_ldst_post(insn)) + offset = 0; + else + offset = *immediate; + + /* First register */ + rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); + ADD_OP(op) { + if (aarch64_insn_is_store_single(insn) || + aarch64_insn_is_store_pair(insn)) + make_store_op(base, rt, offset, op); + else + make_load_op(base, rt, offset, op); + } + + /* Second register (if present) */ + if (aarch64_insn_is_store_pair(insn) || + aarch64_insn_is_load_pair(insn)) { + rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT2, + insn); + ADD_OP(op) { + if (aarch64_insn_is_store_pair(insn)) + make_store_op(base, rt, offset + size, op); + else + make_load_op(base, rt, offset + size, op); + } + } + + if (aarch64_insn_is_ldst_pre(insn) || + aarch64_insn_is_ldst_post(insn)) { + ADD_OP(op) { + make_add_op(base, base, *immediate, op); + } + } + + return 0; +} + static void decode_add_sub_imm(u32 instr, bool set_flags, unsigned long *immediate, struct stack_op *op) @@ -241,6 +349,10 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec *immediate = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn); } break; + case AARCH64_INSN_CLS_LDST: + { + return decode_load_store(insn, immediate, ops_list); + } default: break; }