From patchwork Thu Jun 23 16:03:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 12892886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61605CCA482 for ; Thu, 23 Jun 2022 16:05:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YxJfWePjr0F+o0Y9YszNdqxaAciRaZSQ/T5NqB9w+Ac=; b=NK7+PAEl0NZezT 4KBzISZNv92Tv3dz75hOgBMwbR2P7YXBj6toUoAaZzPsOnYN9JT4k7IWSdJtGYoVjVaoTb1VO8eFG p7xnSm1JNXX3oZMQOAbSMhrLn4Oyf+bX5+ljw4kJg3Y5QVAy4dybyLBjiPLwCe9BxyX6Lv3ZApgKY Y60jdbqGqI53fVtmdQDHGnDBCAQRuTVyR6j9ypA/Qk6tsTwJLuha8IgiFv7MzfumWizEe3qUEYo89 F7NOF4uQFZZTrWA+iNlSR8Ikg86UYcSMq4wNdAfhqvTPphvaNsaJly6K1fRnx1g/afVLRBE+H7z4X jkPvOGAFthBucn/mOrOA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4PJs-00Fnej-GM; Thu, 23 Jun 2022 16:04:36 +0000 Received: from madras.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e5ab]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4PJg-00FncC-CF; Thu, 23 Jun 2022 16:04:26 +0000 Received: from jupiter.universe (unknown [95.33.159.255]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 63D8466017E4; Thu, 23 Jun 2022 17:04:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656000260; bh=JyODDbAkozctO2YF4+4+8QrF0xaiP+MYadCgEeOgwr0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LGglfLaFni5u8gXAQ2JFlRVE1lfhiFRI+lJp2LSBZDn1JEAzJfBs3Q90TkocJaeIa 7hghODJXm5+mrtYT0qLq6djDtK2DNq2AbqQSE0HtBHXhDVrSIv8CedmSpsEnBH1PfS yYEEaaTSWIUOOxbHncdqwQXiWYJ2c+n0sXd98dZ6NwtBzWDfpNuL6XxxHjV5NoNl8Q w5iJyEOblil+/hjQehSoaoWD3nwctT+rMYEl4lDOqEc6GGOrDSNrINNm1597tm6qpP OmSKb+PeV8BgVNWEdWdT0E35YrH4t6kbLmtaCfHoGy19JwdDp45l3dFdvzE6dxAoEk G+jcyKwV6PVIA== Received: by jupiter.universe (Postfix, from userid 1000) id CAB7A48059B; Thu, 23 Jun 2022 18:04:17 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Elaine Zhang , kernel@collabora.com, Sebastian Reichel Subject: [PATCH 4/5] clk: rockchip: clk-cpu: add mux setting for cpu change frequency Date: Thu, 23 Jun 2022 18:03:28 +0200 Message-Id: <20220623160329.239501-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623160329.239501-1-sebastian.reichel@collabora.com> References: <20220623160329.239501-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220623_090425_142259_1CC7138A X-CRM114-Status: GOOD ( 16.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Elaine Zhang In order to improve the main frequency of CPU, the clock path of CPU is simplified as follows: |--\ | \ |--\ --apll--|\ | \ | \ | |--apll_core--| \ | \ --24M---|/ |mux1 |--[gate]--|mux2|---clk_core | / | / --gpll--|\ | / |------| / | |--gpll_core--| / | |--/ --24M---|/ |--/ | | -------apll_directly--------------| When the CPU requests high frequency, we want to use MUX2 select the "apll_directly". At low frequencies use MUX1 to select “apll_core" and then MUX2 to select "apll_core_gate". However, in this way, the CPU frequency conversion needs to be in the following order: 1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core" 2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL sets normal_mode 3. MUX1 select "apll_core", MUX2 select "apll_directly" So add pre_muxs and post_muxs to cover this special requirements. Signed-off-by: Elaine Zhang [rebase] Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk-cpu.c | 41 ++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 2 ++ 2 files changed, 43 insertions(+) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 11aa2259b532..6ea7fba9f9e5 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, } } +static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk, + const struct rockchip_cpuclk_rate_table *rate) +{ + int i; + + /* alternate parent is active now. set the pre_muxs */ + for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) { + const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; + + if (!clksel->reg) + break; + + pr_debug("%s: setting reg 0x%x to 0x%x\n", + __func__, clksel->reg, clksel->val); + writel(clksel->val, cpuclk->reg_base + clksel->reg); + } +} + +static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk, + const struct rockchip_cpuclk_rate_table *rate) +{ + int i; + + /* alternate parent is active now. set the muxs */ + for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) { + const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; + + if (!clksel->reg) + break; + + pr_debug("%s: setting reg 0x%x to 0x%x\n", + __func__, clksel->reg, clksel->val); + writel(clksel->val, cpuclk->reg_base + clksel->reg); + } +} + static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, struct clk_notifier_data *ndata) { @@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, cpuclk->reg_base + reg_data->core_reg[i]); } } + + rockchip_cpuclk_set_pre_muxs(cpuclk, rate); + /* select alternate parent */ if (reg_data->mux_core_reg) writel(HIWORD_UPDATE(reg_data->mux_core_alt, @@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, reg_data->mux_core_shift), cpuclk->reg_base + reg_data->core_reg[0]); + rockchip_cpuclk_set_post_muxs(cpuclk, rate); + /* remove dividers */ for (i = 0; i < reg_data->num_cores; i++) { writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i], diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index bf7c8d082fde..2bd1863a7418 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -380,6 +380,8 @@ struct rockchip_cpuclk_clksel { struct rockchip_cpuclk_rate_table { unsigned long prate; struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; }; /**