From patchwork Fri Jun 24 16:52:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roman Stratiienko X-Patchwork-Id: 12894887 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7971BC43334 for ; Fri, 24 Jun 2022 16:53:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=RsjdouT/59wWDQHOHbLV3sYbwH7djhATL59n5DzSkP4=; b=aD1g+NblrOMB+u dmFdXZfF6PcWS/tT5l3rgWuR03PExYfJzFPYUnX+PRGMtcc+PLXUzBpBGrBIE1vol1mlSVP5aPmNw ZaIeX7XsXrK1LwWqBk+d18EDY2vBkah2MDhfUi1lHTidxBr1m6gHY2UkNxkhtB0jgfWEC84al4uyR ug6enn6wRV+eD9Ur9h4JRlfOnN7QydgDLLGn1CCADY9Ntnv5R89gss9hrlQBEaVvx3509b4bYoyG5 RkA8WFE1aRXBMAC6OrjTnY36O97DCJ7XDwsmw428u0XM0iFP0VeDwwWEHwomK6SgIEmVVSlYFhATt njuwWwJFz28E88bJfW1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4mXj-0034SL-4O; Fri, 24 Jun 2022 16:52:27 +0000 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4mXf-0034QM-5O for linux-arm-kernel@lists.infradead.org; Fri, 24 Jun 2022 16:52:24 +0000 Received: by mail-ej1-x631.google.com with SMTP id ge10so5870269ejb.7 for ; Fri, 24 Jun 2022 09:52:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wbymErIEYkOFeBKk/ebEJiqOJG2qjdsYlqZoWmC7QLE=; b=PRRbdWpwESnTfnifMOyCgpGVdaGmvXQWwSZ3f6whE1ZxjZFa+545KZbP2dWC4hkBEt s8vL/QSlIJgYyoxdYpenaVdfezjz27HCliox/O8r2THavoUObV+SS2MMsEVNQSbOIp+n wCH7a7NFJV2lMsxU+B0haGz6nXtJ8llqqjADcitqejPzY0VyRQQXEgP8v5m/7kwr2Gp1 C0Ymu6A4GldzaR/0OPpjHzgD72fNiKUTcDZ3MUa20hnakwVjsukV94zH2NHIlNVRi5BQ HdKJTKnXWgz7g3LCKr7CKtpz9v/RYj2A5eIXNOLJL35/V4eLwAcxTC5oFnu7ukuIBb70 uv4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wbymErIEYkOFeBKk/ebEJiqOJG2qjdsYlqZoWmC7QLE=; b=azThCoGCKkrfvVqaKoi36cYW7je9QLBVnCXg+Ipcbkvpc9oqlSwvKpj0YZ/BaZdIkc 8bpnwfiutwKbl/jNhDWjjfk/Ak2fQiKItheYXeS1IyYxlkd0nbTlOhO3yHKJZydoatDA lxnknGtQsMChw9mvxQ+Nefq+0T6fUa2WzWryA72XYujW8v/UX3Dd/xCJngtBBBe8UIyf Hl1EUw1SW2aCA8TxWERuteZYyRcx/xCALncfDlaFqTobKhA4ig61luhU2+VOxyEUNDcu Cbm/m5dlb/6pjO+9eYJqA407XlqGlDRKkBoLNRfGWNVkacJWjVRIWBIkpm4KDcTlzqkv pmjA== X-Gm-Message-State: AJIora9EcZeLEGwYftGYgc94YqhOJmEaUYarSqySKO92g5sI+cSJJfIv ywsIAk2yq9zDAI05ii14JiU= X-Google-Smtp-Source: AGRyM1vrLg2W+cGGP3wxtvgoeuzjy++7TyLF+nXPHCinNEq5lfVYYODHu3V1BUQIakLhaOy9dyJ/iw== X-Received: by 2002:a17:907:7249:b0:711:e939:bbb4 with SMTP id ds9-20020a170907724900b00711e939bbb4mr14351418ejc.480.1656089537406; Fri, 24 Jun 2022 09:52:17 -0700 (PDT) Received: from roman-Latitude-3400.globallogic.com ([195.234.74.2]) by smtp.gmail.com with ESMTPSA id b20-20020a0564021f1400b0042e15364d14sm2494479edb.8.2022.06.24.09.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jun 2022 09:52:16 -0700 (PDT) From: Roman Stratiienko To: peron.clem@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, mripard@kernel.org, wens@csie.org, jernej.skrabec@gmail.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Roman Stratiienko Subject: [PATCH] clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS Date: Fri, 24 Jun 2022 19:52:11 +0300 Message-Id: <20220624165211.4318-1-r.stratiienko@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220624_095223_249161_97C48D98 X-CRM114-Status: GOOD ( 13.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Using simple bash script it was discovered that not all CCU registers can be safely used for DFS, e.g.: while true do devmem 0x3001030 4 0xb0003e02 devmem 0x3001030 4 0xb0001e02 done Script above changes the GPU_PLL multiplier register value. While the script is running, the user should interact with the user interface. Using this method the following results were obtained: | Register | Name | Bits | Values | Result | | -- | -- | -- | -- | -- | | 0x3001030 | GPU_PLL.MULT | 15..8 | 20-62 | OK | | 0x3001030 | GPU_PLL.INDIV | 1 | 0-1 | OK | | 0x3001030 | GPU_PLL.OUTDIV | 0 | 0-1 | FAIL | | 0x3001670 | GPU_CLK.DIV | 3..0 | ANY | FAIL | Once bits that caused system failure disabled (kept default 0), it was discovered that GPU_CLK.MUX was used during DFS for some reason and was causing the failure too. After disabling GPU_PLL.OUTDIV the system started to fail during booting for some reason until the maximum frequency of GPU_PLL clock was limited to 756MHz. After all the changes made DVFS started to work seamlessly. Signed-off-by: Roman Stratiienko --- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 2ddf0a0da526f..d941238cd178a 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -95,13 +95,14 @@ static struct ccu_nkmp pll_periph1_clk = { }, }; +/* For GPU PLL, using an output divider for DFS causes system to fail */ #define SUN50I_H6_PLL_GPU_REG 0x030 static struct ccu_nkmp pll_gpu_clk = { .enable = BIT(31), .lock = BIT(28), .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ - .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ + .max_rate = 756000000UL, .common = { .reg = 0x030, .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", @@ -294,12 +295,9 @@ static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2", 0x62c, BIT(0), 0); -static const char * const gpu_parents[] = { "pll-gpu" }; -static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, - 0, 3, /* M */ - 24, 1, /* mux */ - BIT(31), /* gate */ - CLK_SET_RATE_PARENT); +/* GPU_CLK divider kept disabled to avoid interferences with DFS */ +static SUNXI_CCU_GATE(gpu_clk, "gpu", "pll-gpu", 0x670, + BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", 0x67c, BIT(0), 0);