| Message ID | 20220626021148.56740-3-samuel@sholland.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | pinctrl: sunxi: Allwinner D1/D1s support | expand |
Dne nedelja, 26. junij 2022 ob 04:11:43 CEST je Samuel Holland napisal(a): > H6 requires I/O bias configuration on both of its PIO devices. > Previously it was only done for the main PIO. > > The setting for Port L is at bit 0, so the bank calculation needs to > account for the pin base. Otherwise the wrong bit is used. > > Fixes: cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on > H6") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Did you noticed any improvement with this properly set? In theory, 3.3 V bias should always work, right? Best regards, Jernej
On 6/27/22 3:34 PM, Jernej Škrabec wrote: > Dne nedelja, 26. junij 2022 ob 04:11:43 CEST je Samuel Holland napisal(a): >> H6 requires I/O bias configuration on both of its PIO devices. >> Previously it was only done for the main PIO. >> >> The setting for Port L is at bit 0, so the bank calculation needs to >> account for the pin base. Otherwise the wrong bit is used. >> >> Fixes: cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on >> H6") Signed-off-by: Samuel Holland <samuel@sholland.org> > > Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> > > Did you noticed any improvement with this properly set? In theory, 3.3 V bias > should always work, right? I think it matters for inputs, which may not detect a high level state if the bias (comparator reference) voltage is too high. It looks like Orange Pi 3 has a 1.8 V supply for port M. I am not currently set up to test the behavior with different bias settings, but I may do that if I get the chance. Regards, Samuel
Am Sonntag, 26. Juni 2022, 04:11:43 CEST schrieb Samuel Holland: > H6 requires I/O bias configuration on both of its PIO devices. > Previously it was only done for the main PIO. > > The setting for Port L is at bit 0, so the bank calculation needs to > account for the pin base. Otherwise the wrong bit is used. > > Fixes: cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on H6") > Signed-off-by: Samuel Holland <samuel@sholland.org> On a D1-Nezha Tested-by: Heiko Stuebner <heiko@sntech.de>
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c index c7d90c44e87a..7b4b9f3d4555 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c @@ -107,6 +107,7 @@ static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = { .npins = ARRAY_SIZE(sun50i_h6_r_pins), .pin_base = PL_BASE, .irq_banks = 2, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index d9327d7d56ee..3c5e71359ca8 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -622,7 +622,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, unsigned pin, struct regulator *supply) { - unsigned short bank = pin / PINS_PER_BANK; + unsigned short bank; unsigned long flags; u32 val, reg; int uV; @@ -638,6 +638,9 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, if (uV == 0) return 0; + pin -= pctl->desc->pin_base; + bank = pin / PINS_PER_BANK; + switch (pctl->desc->io_bias_cfg_variant) { case BIAS_VOLTAGE_GRP_CONFIG: /* @@ -655,8 +658,6 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, else val = 0xD; /* 3.3V */ - pin -= pctl->desc->pin_base; - reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); reg &= ~IO_BIAS_MASK; writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
H6 requires I/O bias configuration on both of its PIO devices. Previously it was only done for the main PIO. The setting for Port L is at bit 0, so the bank calculation needs to account for the pin base. Otherwise the wrong bit is used. Fixes: cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on H6") Signed-off-by: Samuel Holland <samuel@sholland.org> --- drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 1 + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-)