diff mbox series

iommu/arm-smmu-v3: Fix undefined behavior in GBPA_UPDATE

Message ID 20220630063959.27226-1-burzalodowa@gmail.com (mailing list archive)
State New, archived
Headers show
Series iommu/arm-smmu-v3: Fix undefined behavior in GBPA_UPDATE | expand

Commit Message

Xenia Ragiadakou June 30, 2022, 6:39 a.m. UTC
The expression 1 << 31 results in undefined behaviour because the type of
integer constant 1 is (signed) int and the result of shifting 1 by 31 bits
is not representable in the (signed) int type.

Change the type of 1 to unsigned int by adding the U suffix.

Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Will Deacon July 1, 2022, 2:34 p.m. UTC | #1
On Thu, Jun 30, 2022 at 09:39:59AM +0300, Xenia Ragiadakou wrote:
> The expression 1 << 31 results in undefined behaviour because the type of
> integer constant 1 is (signed) int and the result of shifting 1 by 31 bits
> is not representable in the (signed) int type.
> 
> Change the type of 1 to unsigned int by adding the U suffix.
> 
> Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com>
> ---
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> index cd48590ada30..44fbd499edea 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> @@ -96,7 +96,7 @@
>  #define CR2_E2H				(1 << 0)
>  
>  #define ARM_SMMU_GBPA			0x44
> -#define GBPA_UPDATE			(1 << 31)
> +#define GBPA_UPDATE			(1U << 31)

There are loads of these kicking around in the kernel sources and we compile
with -fno-strict-overflow.

If you really want to change these, then let's use the BIT() macro instead,
but I think it's really just churn.

Will
Xenia Ragiadakou July 1, 2022, 4:13 p.m. UTC | #2
On 7/1/22 17:34, Will Deacon wrote:
> On Thu, Jun 30, 2022 at 09:39:59AM +0300, Xenia Ragiadakou wrote:
>> The expression 1 << 31 results in undefined behaviour because the type of
>> integer constant 1 is (signed) int and the result of shifting 1 by 31 bits
>> is not representable in the (signed) int type.
>>
>> Change the type of 1 to unsigned int by adding the U suffix.
>>
>> Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com>
>> ---
>>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
>> index cd48590ada30..44fbd499edea 100644
>> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
>> @@ -96,7 +96,7 @@
>>   #define CR2_E2H				(1 << 0)
>>   
>>   #define ARM_SMMU_GBPA			0x44
>> -#define GBPA_UPDATE			(1 << 31)
>> +#define GBPA_UPDATE			(1U << 31)
> There are loads of these kicking around in the kernel sources and we compile
> with -fno-strict-overflow.
>
> If you really want to change these, then let's use the BIT() macro instead,
> but I think it's really just churn.
>
> Will
Hi Will,

I thought that since in commit 587e6c10a7ce89a5924fdbeff2ec524fbd6a124b 
there was a similar fix to Q_OVERFLOW_FLAG (see below)

--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -183,7 +183,7 @@

  #define Q_IDX(llq, p)                  ((p) & ((1 << 
(llq)->max_n_shift) - 1))
  #define Q_WRP(llq, p)                  ((p) & (1 << (llq)->max_n_shift))
-#define Q_OVERFLOW_FLAG                        (1 << 31)
+#define Q_OVERFLOW_FLAG                        (1U << 31)
  #define Q_OVF(p)                       ((p) & Q_OVERFLOW_FLAG)
  #define Q_ENT(q, p)                    ((q)->base +                    \
                                          Q_IDX(&((q)->llq), p) *        \

then it would make sense to fix GBPA_UPDATE in the same way.

Xenia
diff mbox series

Patch

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index cd48590ada30..44fbd499edea 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -96,7 +96,7 @@ 
 #define CR2_E2H				(1 << 0)
 
 #define ARM_SMMU_GBPA			0x44
-#define GBPA_UPDATE			(1 << 31)
+#define GBPA_UPDATE			(1U << 31)
 #define GBPA_ABORT			(1 << 20)
 
 #define ARM_SMMU_IRQ_CTRL		0x50