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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2022 11:00:29.5624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbd88fb3-aa76-4aff-48cd-08da5a87beee X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT021.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB5665 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220630_040033_760918_EDA99826 X-CRM114-Status: GOOD ( 11.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org __cpu_setup() used `vabits_actual` before it had been set to the correct value (in arm64_memblock_init()), if 52-bit address space was supported. Use the register value directly so that TCR_EL1.T1SZ will be set to the correct value. This fixes booting on QEMU and the FVP model. Fixes: 0d9b1ffefabe ("arm64: mm: make vabits_actual a build time constant if possible") Signed-off-by: Joey Gouly Cc: Ard Biesheuvel Cc: Will Deacon Cc: Anshuman Khandual Cc: Mark Rutland Signed-off-by: Joey Gouly --- arch/arm64/mm/proc.S | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 605c6640f94b..375448b2de9e 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -466,7 +466,16 @@ SYM_FUNC_START(__cpu_setup) tcr_clear_errata_bits tcr, x9, x5 #ifdef CONFIG_ARM64_VA_BITS_52 - ldr_l x9, vabits_actual + /* + * vabits_actual has not been set at this point, check the + * ID_AA64MMFR2_EL1 register directly. + */ + mrs_s x10, SYS_ID_AA64MMFR2_EL1 + and x10, x10, #(0xf << ID_AA64MMFR2_LVA_SHIFT) + mov x9, #52 + cbnz x10, 1f + mov x9, #VA_BITS_MIN +1: sub x9, xzr, x9 add x9, x9, #64 tcr_set_t1sz tcr, x9