From patchwork Mon Jul 4 08:11:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12904838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F00B4C43334 for ; Mon, 4 Jul 2022 08:16:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CrxdL0DqVKDPLzH9VvjvYqcXqU2dGnFIcWe9hSDtH6o=; b=gKnU0u4hH1W/4T brJ/LLKF23+wcx+jeiNwikdfTkUT7K0nTpETuZXY5oMR0OmS/WWIjzW57dY+jmPotGVU3aAj4O5TU s7GYlFg92XcN0xbx7CgjoBaRN+US07NJGs2AcP4jKHwQq8RFdNONTpxNuoV2Lqlwv+y2rWPqEMZBl gGeyL17Pvo4NB/DqsLFx86rmXeGsj3qwACAUNq7mYW9BsMTeiltu91j6PEW3t+ieYu9J8QB9Dmuy6 fC3RiD+MERRQ+Ou2MF/0JnAhYgRUFYKNFUgkZIBH4pdmLhfXr0XI4Mo3X/HkYvzy89AthELrfdIq7 6yr3U3ZsM4nNniXxdSmg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8HEr-005zSG-30; Mon, 04 Jul 2022 08:15:25 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8HBc-005xpu-21 for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 08:12:09 +0000 Received: by mail-wm1-x336.google.com with SMTP id 205-20020a1c02d6000000b003a03567d5e9so7021263wmc.1 for ; Mon, 04 Jul 2022 01:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O0T6iSxIoNn8Gu/FxWaC6WvogLfn9QCdL/z8tiUr0ks=; b=N2WHXyk2+zP/vYzR1T2MOhfZGFijkVFfzaRR82FrfOQGY/7ezaU7j94KlC1Z///RDR UFu6dTuPwMYttwKj1Nht5wSahuHlIIHV5VhsuUQE8qLT+pZNg88pzqnXVOQIQ75DwoxD c1aKGMXgzHh7g8kPCGAY8iNqbuoGicdN06m3BPmxiLlTVJ8na0slgJdSwpSVRHoQtZIm GuZobYP4jnz7keEPEhN2X3L+1ufXKg6dmI+c+yp64AvTKnYiWtglUIW8qGLkTtRuiTAW Z5VvYlU4Vos+eGePHzw1CFLKfrWkFq2T4C27sRuzweoYaHwiBuff5d+4T6kEyedfSn0j 2Jqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=O0T6iSxIoNn8Gu/FxWaC6WvogLfn9QCdL/z8tiUr0ks=; b=p8kkIfATqwWyuKSTcEDKQbnPl7Vd6z4nzxlS2wQaBKNnCJaj/P4szLoTTdL7i9bMP9 1DRkGVJ6Tc0yp1XgjGU8dSzeeOAybH4okiRqsbQssRwMVoRUUBI5gNhEZHKylSk7h7IF iew0mViogZKv0dXRGEUdxIm7uw2UAyzWjhyMosmCvlBOuogEsDrQJYvC4VHJ/9chCvT0 tP9UMQvM57CNXNFPxDMNnLW5fPazmLI0XqCybzlQS5o/nsEaQQ0JSblCSQBJDPDGWCLH Q7Vq0677eM61ZeJAyoBlRnWPfGwYbAaZ/zI0wK2PkRHXTce/zAI6qZJNHdS6q/FlXF31 XS6g== X-Gm-Message-State: AJIora8Pf+jvzIr+Dq6GqBWN82zz7tI0LmvMPNOEGuDXDRzoLJRE0z1E TIri8XqboFiyaKCrxfILY+hxyA== X-Google-Smtp-Source: AGRyM1vyZRYXOjBVB9DRfkXD+EUlfDYeLN4AeTBJSnU/FigvnmKIqmrXouU3ruaOFHQTpcPFSAOd1g== X-Received: by 2002:a05:600c:3d96:b0:3a1:8681:cc80 with SMTP id bi22-20020a05600c3d9600b003a18681cc80mr22311366wmb.192.1656922320417; Mon, 04 Jul 2022 01:12:00 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:c4c4:4ed1:ae43:27f2]) by smtp.gmail.com with ESMTPSA id u3-20020adfdd43000000b0021d650e4df4sm4388276wrm.87.2022.07.04.01.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jul 2022 01:11:59 -0700 (PDT) From: Mike Leach To: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v2 09/13] perf: cs-etm: Update record event to use new Trace ID protocol Date: Mon, 4 Jul 2022 09:11:45 +0100 Message-Id: <20220704081149.16797-10-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220704081149.16797-1-mike.leach@linaro.org> References: <20220704081149.16797-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_011204_180806_D48D456A X-CRM114-Status: GOOD ( 21.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Trace IDs are now dynamically allocated. Previously used the static association algorithm that is no longer used. The 'cpu * 2 + seed' was outdated and broken for systems with high core counts (>46). as it did not scale and was broken for larger core counts. Trace ID is as unknown in AUXINFO record, and the ID / CPU association will now be sent in PERF_RECORD_AUX_OUTPUT_HW_ID record. Remove legacy Trace ID allocation algorithm. Signed-off-by: Mike Leach --- include/linux/coresight-pmu.h | 19 +++++++------------ tools/include/linux/coresight-pmu.h | 19 +++++++------------ tools/perf/arch/arm/util/cs-etm.c | 21 ++++++++++++--------- 3 files changed, 26 insertions(+), 33 deletions(-) diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 4ac5c081af93..9f7ee380266b 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -8,7 +8,13 @@ #define _LINUX_CORESIGHT_PMU_H #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 + +/* + * Metadata now contains an unused trace ID - IDs are transmitted using a + * PERF_RECORD_AUX_OUTPUT_HW_ID record. + * Value architecturally defined as reserved in CoreSight. + */ +#define CS_UNUSED_TRACE_ID 0x7F /* * Below are the definition of bit offsets for perf option, and works as @@ -32,15 +38,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 6c2fd6cc5a98..31d007fab3a6 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -8,7 +8,13 @@ #define _LINUX_CORESIGHT_PMU_H #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 + +/* + * Metadata now contains an unused trace ID - IDs are transmitted using a + * PERF_RECORD_AUX_OUTPUT_HW_ID record. + * Value architecturally defined as reserved in CoreSight. + */ +#define CS_UNUSED_TRACE_ID 0x7F /* * Below are the definition of bit offsets for perf option, and works as @@ -34,15 +40,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 1b54638d53b0..2d68e6a722ed 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -421,13 +421,16 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, evlist__to_front(evlist, cs_etm_evsel); /* - * In the case of per-cpu mmaps, we need the CPU on the - * AUX event. We also need the contextID in order to be notified + * get the CPU on the sample - need it to associate trace ID in the + * AUX_OUTPUT_HW_ID event, and the AUX event for per-cpu mmaps. + */ + evsel__set_sample_bit(cs_etm_evsel, CPU); + + /* + * Also the case of per-cpu mmaps, need the contextID in order to be notified * when a context switch happened. */ if (!perf_cpu_map__empty(cpus)) { - evsel__set_sample_bit(cs_etm_evsel, CPU); - err = cs_etm_set_option(itr, cs_etm_evsel, BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_TS)); if (err) @@ -633,8 +636,9 @@ static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, /* Get trace configuration register */ data[CS_ETMV4_TRCCONFIGR] = cs_etmv4_get_config(itr); - /* Get traceID from the framework */ - data[CS_ETMV4_TRCTRACEIDR] = coresight_get_trace_id(cpu); + /* traceID set to unused */ + data[CS_ETMV4_TRCTRACEIDR] = CS_UNUSED_TRACE_ID; + /* Get read-only information from sysFS */ data[CS_ETMV4_TRCIDR0] = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]); @@ -681,9 +685,8 @@ static void cs_etm_get_metadata(int cpu, u32 *offset, magic = __perf_cs_etmv3_magic; /* Get configuration register */ info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr); - /* Get traceID from the framework */ - info->priv[*offset + CS_ETM_ETMTRACEIDR] = - coresight_get_trace_id(cpu); + /* traceID set to unused */ + info->priv[*offset + CS_ETM_ETMTRACEIDR] = CS_UNUSED_TRACE_ID; /* Get read-only information from sysFS */ info->priv[*offset + CS_ETM_ETMCCER] = cs_etm_get_ro(cs_etm_pmu, cpu,