From patchwork Wed Jul 6 11:06:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12907982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC087CCA473 for ; Wed, 6 Jul 2022 11:08:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h/118D+KMv36U2+pApGd/xUk+2OAB0NBjP67Xu3AtTw=; b=r/VhbwvEa9BKtu RkQ5K8BzYmrXn2MO3y33eFG5oc19ab56cM3RuNouYWul5V2A1ZFWR7L/LwY1HMkRplXifV4dtNQJH FTWLkMosejUCmYsmiX10OpFGIGTrJxhkz7T4d4xO6LGgW0La6iTPV8Td3+Tgzxt3cl/VP+PSjFEA9 w1gz6ywWOGV3acZ0YdbYAnFO4pRU+eF6loVD/MDpnhK9HaZ4+FIWKYv0EZcIN7sGx2aGbVD4DoitE 3uZxyY7XnSjQCrFrKcpM94ZrZ26CTzEb0AN2Svs2D8fr8sA/XSf1ThD//TQCBkgYGYEp62aCu3HbM paoXE5tg6CP12gv+Uu6g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o92sI-009907-2k; Wed, 06 Jul 2022 11:07:18 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o92sB-0098tK-N5 for linux-arm-kernel@lists.infradead.org; Wed, 06 Jul 2022 11:07:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657105631; x=1688641631; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d6++wd2M1ULC9f+tZJMZhP48bnLFY5Pba7B8hjFDzyc=; b=TRti21HkHQhJNLdJY/5EBiCu7KWzKAFokJtYSXVnIRI5UZwmraNcYlpS I21VzNpJ1a8fZ/HiUON1qQ5BmtatrmaTBS+wvQdA/t13/i9ZayANTaD0Y iFsFAOYi2UHy8ZcX+fp2r1Hvb6Y4UNuCUIxYaIvj8u/1Zo0Rvtebu3fIy Uptdo8VrDV0cXzcwHyIUxd5k2FrTPPPmIgD1gSdUPc9kalNYkTZU+OU6S jkt7dz6+l9nRaBRpxpyAxg4Mi5Y5MTeGahzWCdpxzsPbluSeoC/sCePii H6/cFpyWW/hZ6AwuSnwwiNKU04Eht1EyENInE1FaDQu1tPfoRs/pca+nd A==; X-IronPort-AV: E=Sophos;i="5.92,249,1650956400"; d="scan'208";a="103261638" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Jul 2022 04:06:55 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 6 Jul 2022 04:06:54 -0700 Received: from kavya.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 6 Jul 2022 04:06:50 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , Subject: [PATCH v7 2/3] dt-bindings: mfd: atmel,sama5d2-flexcom: Add new compatible string for lan966x Date: Wed, 6 Jul 2022 09:06:18 -0200 Message-ID: <20220706110619.71729-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220706110619.71729-1-kavyasree.kotagiri@microchip.com> References: <20220706110619.71729-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220706_040711_859574_620FF6DB X-CRM114-Status: GOOD ( 10.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri --- v6 -> v7: - Add #address-cells, #size-cells to flx3 example. v5 -> v6: - Removed spi node from flx3 example. v4 -> v5: - Fixed indentations and dt-schema errors. - No errors seen with 'make dt_binding_check'. v3 -> v4: - Added else condition to allOf:if:then. v2 -> v3: - Add reg property of lan966x missed in v2. v1 -> v2: - Use allOf:if:then for lan966x dt properties .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 65 ++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 864f490ffb83..b4b47accab49 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -18,9 +18,11 @@ properties: compatible: enum: - atmel,sama5d2-flexcom + - microchip,lan966x-flexcom reg: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: maxItems: 1 @@ -47,6 +49,27 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3] + microchip,flx-shrd-pins: + description: Specify the Flexcom shared pins to be used for flexcom + chip-selects. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 20 + + microchip,flx-cs: + description: Flexcom chip selects. Here, value of '0' represents "cts" line + of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents + "rts" line of flexcom USART or "cs1" line of flexcom SPI. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + required: - compatible - reg @@ -56,6 +79,31 @@ required: - ranges - atmel,flexcom-mode +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan966x-flexcom + + then: + properties: + reg: + items: + - description: Flexcom base registers map + - description: Flexcom shared registers map + required: + - microchip,flx-shrd-pins + - microchip,flx-cs + + else: + properties: + reg: + items: + - description: Flexcom base registers map + microchip,flx-shrd-pins: false + microchip,flx-cs: false + additionalProperties: false examples: @@ -71,4 +119,19 @@ examples: ranges = <0x0 0xf8034000 0x800>; atmel,flexcom-mode = <2>; }; + - | + #include + + flx3: flexcom@e0064000 { + compatible = "microchip,lan966x-flexcom"; + reg = <0xe0064000 0x100>, + <0xe2004180 0x8>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + atmel,flexcom-mode = <2>; + microchip,flx-shrd-pins = <9>; + microchip,flx-cs = <0>; + }; ...