From patchwork Thu Jul 7 13:24:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12909584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DF2BC43334 for ; Thu, 7 Jul 2022 13:26:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=xGTVCyglvUrA1r22y91QzNfCIXM9SWk08CYjP5Dmbzg=; b=VGe2620qBHt5V1 /i9uM4PbkOAWiCXs6yrZIih5l6u3ACbOlGTwGPTtFpaTxFQm2u9QVbC9e1KB5h5Oj1UeW9c+MVBbP TeWwBRObxcOCXVA5heOJhm7P8H1z131BahblOJJ2vqO51CsYbkqH290EvntRboxZZ2pJFWCBGxrWU Aar+cfSs+HjPiIZ5BCLtQ9N2A94GSI407V8WUylrZoV1I6aMJSkS6/SCkp+SufcRyDp5thXNBXgF+ euewQ1f+UGD3XKsVbXMI1+PfiDxeOY6Jj6+1c35ndnvQZUFNxx4iPraJjumYGpvMdLQgUalwl+2i2 GY2TSYYxxOsJDJB3T0VQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o9RVb-00GF7V-0A; Thu, 07 Jul 2022 13:25:31 +0000 Received: from ssl.serverraum.org ([2a01:4f8:151:8464::1:2]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o9RVH-00GF0M-Dj for linux-arm-kernel@lists.infradead.org; Thu, 07 Jul 2022 13:25:12 +0000 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id ABDD12222E; Thu, 7 Jul 2022 15:25:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1657200306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=g0df1sTvycQkJsdAtaM7OC4dv6nK2I/GrDWXYw1cHHA=; b=LcylVWLk0BwLEFqQurrO71hN1dEXkvt/UZoImbS+g3lQWNkPL2tRhXpyjhTaCq+Rtt2ruS gNPXoCxV94axEgDjbX8l7c7JRo5atQoj0QxrTTjy6ECVfRezEshpHMkTE06UtuiXgEdwqF sCEHXddGOaFL8+41VSOYIJuFl868GxE= From: Michael Walle To: Rob Herring , Krzysztof Kozlowski , Claudiu Beznea , Nicolas Ferre , Alexandre Belloni Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH v2 1/2] ARM: dts: lan966x: add clock gating register Date: Thu, 7 Jul 2022 15:24:59 +0200 Message-Id: <20220707132500.1708020-1-michael@walle.cc> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220707_062511_718887_5B325F07 X-CRM114-Status: GOOD ( 11.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The clock controller supports an optional clock gating register. This is necessary to expose the USB device clock, for example. Add it. Signed-off-by: Michael Walle --- changes since v1: - none arch/arm/boot/dts/lan966x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 57cb67a180ec..bc102677ff91 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -65,7 +65,7 @@ clks: clock-controller@e00c00a8 { #clock-cells = <1>; clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; clock-names = "cpu", "ddr", "sys"; - reg = <0xe00c00a8 0x38>; + reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; }; timer {