diff mbox series

[v3,1/2] ARM: Remove AES hwcap for parts affected by errata

Message ID 20220714161523.279570-2-james.morse@arm.com (mailing list archive)
State New, archived
Headers show
Series arm64: errata: Remove AES hwcap for COMPAT tasks | expand

Commit Message

James Morse July 14, 2022, 4:15 p.m. UTC 
Cortex-A57 and Cortex-A72 have an erratum where an interrupt that
occurs between a pair of AES instructions in aarch32 mode may corrupt
the ELR. The task will subsequently produce the wrong AES result.

The AES instructions are part of the cryptographic extensions, which are
optional. User-space software will detect the support for these
instructions from the hwcaps. If the platform doesn't support these
instructions a software implementation should be used.

Remove the hwcap bits on affected parts to indicate user-space should
not use the AES instructions.

A57's r0p0 is not affected, add a read_cpuid_variant() helper and
check the revision and variant.

Acked-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
---
 arch/arm/include/asm/cputype.h |  5 +++++
 arch/arm/kernel/setup.c        | 10 ++++++++++
 2 files changed, 15 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 775cac3c02bb..5b28611ed459 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -223,6 +223,11 @@  static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 	return (read_cpuid_id() & 0xFF000000) >> 24;
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_variant(void)
+{
+	return read_cpuid_id() & 0x00f00000;
+}
+
 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
 {
 	return read_cpuid_id() & 0x0000000f;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1e8a50a97edf..470fa860cd7d 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -501,6 +501,16 @@  static void __init elf_hwcap_fixup(void)
 		return;
 	}
 
+	/*
+	 * HWCAP2_AES can get the wrong result due to A57's erratum #1742098 or
+	 * A72's #1655431. A57 r0p0 is not affected.
+	 */
+	if ((read_cpuid_part() == ARM_CPU_PART_CORTEX_A57 &&
+	     read_cpuid_variant() != 0 && read_cpuid_revision() != 0) ||
+	    read_cpuid_part() == ARM_CPU_PART_CORTEX_A72) {
+		elf_hwcap2 &= ~HWCAP2_AES;
+	}
+
 	/* Verify if CPUID scheme is implemented */
 	if ((id & 0x000f0000) != 0x000f0000)
 		return;